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HAL/vmm_hw_rtl.sv unexpanded source
00001: // 00002: // ------------------------------------------------------------- 00003: // Copyright 2004-2008 Synopsys, Inc. 00004: // All Rights Reserved Worldwide 00005: // 00006: // Licensed under the Apache License, Version 2.0 (the 00007: // "License"); you may not use this file except in 00008: // compliance with the License. You may obtain a copy of 00009: // the License at 00010: // 00011: // http://www.apache.org/licenses/LICENSE-2.0 00012: // 00013: // Unless required by applicable law or agreed to in 00014: // writing, software distributed under the License is 00015: // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 00016: // CONDITIONS OF ANY KIND, either express or implied. See 00017: // the License for the specific language governing 00018: // permissions and limitations under the License. 00019: // ------------------------------------------------------------- 00020: // 00021: 00022: 00025: `define VMM_HW_RTL__SV 00026: 00027: 00028: // 00029: // Select the target architecture 00030: // 00031: `undef VMM_HW_ARCH 00032: 00041: 00042: 00044: // Throw a syntax error if more than one architecture was selected 00049: `define VMM_HW_ARCH 00050: `undef VMM_HW_RTL_USE_MODULE 00052: 00053: 00054: // Throw a syntax error if no architecture was selected 00059: 00060: 00061: // If for simulation, always use an interface 00064: `undef VMM_HW_RTL_USE_MODULE 00066: 00067: 00068: // Include the DUT if mapping to hardware platform (ie. synthesis) 00069: // or using the NULL architecture 00074: `define VMM_HW_INCL_DUT 00076: 00077: 00082: `define VMM_HW_RTL_COMPONENT_START interface : 00083: `define VMM_HW_RTL_COMPONENT_END endinterface : 00085: 00086: 00087: // 00088: //------------------------------------------------------------------ 00089: // 00091: module vmm_hw(); 00092: 00093: reg uclk; 00094: reg urst; 00095: reg crst; 00096: time stamp; 00097: 00098: int reset_cycles = 8; 00099: 00100: initial 00101: begin 00102: stamp = 0; 00103: uclk = 0; 00104: 00105: forever begin 00106: #1 uclk = 1; 00107: stamp = stamp + 1; 00108: #1 uclk = 0; 00109: end 00110: end 00111: 00112: initial 00113: begin 00114: urst = 1; 00115: crst = 0; 00116: repeat (5) @ (posedge uclk); 00117: crst <= 1'b1; 00118: repeat (5) @ (posedge uclk); 00119: urst <= 0; 00120: repeat (reset_cycles * 2) @ (posedge uclk); 00121: crst <= 1'b0; 00122: end 00123: 00124: initial 00125: begin 00126: end 00127: 00128: endmodule 00130: 00131: 00132: // 00133: //------------------------------------------------------------------ 00134: // 00135: 00136: 00137: interface vmm_hw_in_if(rx_rdy, tx_rdy, msg, uclk, urst); 00138: 00139: parameter width = 1; 00140: 00141: input rx_rdy; 00142: output tx_rdy; 00143: output [width-1:0] msg; 00144: input uclk; 00145: input urst; 00146: 00149: integer size = width; 00150: string path = $psprintf("%m"); 00151: reg [1024*8-1:0] ovpath = $psprintf("%m"); // For OV 00153: 00155: // synthesis translate_off 00156: vmm_log log = new("vmm_hw_in_if", $psprintf("%m")); 00157: bit in_use = 0; 00158: 00159: reg tx_rdy; 00160: reg [width-1:0] msg; 00161: 00162: clocking ck @(posedge uclk); 00163: input rx_rdy; 00164: endclocking 00165: 00166: // synthesis translate_on 00168: 00176: 00177: endinterface 00178: 00179: 00180: 00181: // 00182: //------------------------------------------------------------------ 00183: // 00184: interface vmm_hw_out_if(tx_rdy, rx_rdy, msg, uclk, urst); 00185: parameter width = 1; 00186: parameter pri = 10; 00187: 00188: input tx_rdy; 00189: output rx_rdy; 00190: input [width-1:0] msg; 00191: input uclk; 00192: input urst; 00193: 00194: 00197: integer size = width; 00198: string path = $psprintf("%m"); 00200: 00202: // synthesis translate_off 00203: vmm_log log = new("vmm_hw_out_if", $psprintf("%m")); 00204: bit in_use = 0; 00205: 00206: reg rx_rdy; 00207: 00208: clocking ck @(posedge uclk); 00209: input tx_rdy; 00210: input msg; 00211: endclocking 00212: 00213: // synthesis translate_on 00215: 00216: 00224: 00225: endinterface 00226: 00227: 00228: 00229: // 00230: //------------------------------------------------------------------ 00231: // 00232: interface vmm_hw_clock_control(uclk, urst, 00233: rdy_for_cclk, cclk_en, 00234: rdy_for_cclk_neg, cclk_neg_en); 00235: parameter clock_num = 1; 00236: 00237: output uclk; 00238: output urst; 00239: input rdy_for_cclk; 00240: output cclk_en; 00241: input rdy_for_cclk_neg; 00242: output cclk_neg_en; 00243: 00245: // synthesis translate_off 00246: // Make sure uclk and cclk are delta-cycle aligned 00247: reg uclk, urst; 00248: always @(vmm_hw.uclk) uclk <= vmm_hw.uclk; 00249: always @(vmm_hw.urst) urst <= vmm_hw.urst; 00250: // synthesis translate_on 00251: 00252: reg cclk_en; 00253: reg cclk_neg_en; 00254: string path = $psprintf("%M"); 00255: 00256: initial 00257: begin 00258: repeat (2) @ (posedge uclk); 00259: if (cclk_en === 1'bx || cclk_neg_en === 1'bx) begin 00260: $write("ERROR: clock controller %m is not associated with a clock source\n"); 00261: $finish(); 00262: end 00263: end 00265: 00274: 00275: endinterface 00276: 00277: 00278: // 00279: //------------------------------------------------------------------ 00280: // 00281: interface vmm_hw_clock(cclk, crst, crstn); 00282: parameter clock_num = 1; 00283: 00284: parameter ratio_numerator = 1; 00285: parameter ratio_denominator = 1; 00286: parameter duty_hi = 0; 00287: parameter duty_lo = 100; 00288: parameter phase = 0; 00289: parameter reset_cycles = 8; 00290: 00291: output cclk; 00292: output crst, crstn; 00293: 00294: 00296: assign crst = vmm_hw.crst; 00297: assign crstn = ~vmm_hw.crst; 00298: 00299: int no_pos = 0; // For SV 00300: int no_neg = 0; // For SV 00301: wor no_posw; // For Openvera 00302: wor no_negw; // For Openvera 00303: 00304: bit ck_en; 00305: bit ckn_en; 00306: 00307: reg cclk = 0; 00308: 00309: // Controlled clocks must run while ccrst is asserted 00310: assign ck_en = (vmm_hw.urst === 1'b0) && (cclk == 1'b0) && 00311: ((no_pos == 0 && no_posw === 1'bz) || crst); 00312: assign ckn_en = (vmm_hw.urst === 1'b0) && (cclk == 1'b1) && 00313: ((no_neg == 0 && no_negw === 1'bz) || crst); 00314: 00315: initial 00316: begin 00317: if (vmm_hw.reset_cycles < reset_cycles) begin 00318: vmm_hw.reset_cycles = reset_cycles; 00319: end 00320: 00321: if (ratio_numerator != ratio_denominator) begin 00322: $write("WARNING: Unsupported ratio for clock source %M: %0d/%0d (must be 1/1)\n", 00323: ratio_numerator, ratio_denominator); 00324: end 00325: if (duty_hi != 0 && duty_lo != 0) begin 00326: $write("WARNING: Unsupported duty cycle for clock source %M: %0d/%0d (must be 0/x or x/0)\n", 00327: duty_hi, duty_lo); 00328: end 00329: if (phase != 0) begin 00330: $write("WARNING: Unsupported phase for clock source %M: %0d (must be 0)\n", 00331: phase); 00332: end 00333: end 00334: 00335: always @ (posedge vmm_hw.uclk) 00336: begin 00337: if (vmm_hw.urst) cclk <= 1'b0; 00338: else begin 00339: if (ck_en) cclk <= 1'b1; 00340: if (ckn_en) cclk <= 1'b0; 00341: end 00342: end 00343: 00344: string controller[$]; 00345: logic rdy_pos[$]; 00346: logic rdy_neg[$]; 00347: 00348: function void why(); 00349: if (controller.size() == 0) begin 00350: $write("Clock source %M does not have any associated controllers\n"); 00351: return; 00352: end 00353: $write("State of controllers associated with %M:\n"); 00354: $write(" Pos Neg :: Instance\n"); 00355: foreach(controller[i]) begin 00356: $write(" %b %b :: %s\n", rdy_pos[i], rdy_neg[i], controller[i]); 00357: end 00358: endfunction: why 00359: 00361: 00362: 00372: 00373: endinterface 00374: