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00001: //
00002: // -------------------------------------------------------------
00003: // Copyright 2004-2008 Synopsys, Inc.
00004: // All Rights Reserved Worldwide
00005: //
00006: // Licensed under the Apache License, Version 2.0 (the
00007: // "License"); you may not use this file except in
00008: // compliance with the License. You may obtain a copy of
00009: // the License at
00010: //
00011: // http://www.apache.org/licenses/LICENSE-2.0
00012: //
00013: // Unless required by applicable law or agreed to in
00014: // writing, software distributed under the License is
00015: // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
00016: // CONDITIONS OF ANY KIND, either express or implied. See
00017: // the License for the specific language governing
00018: // permissions and limitations under the License.
00019: // -------------------------------------------------------------
00020: //
00021:
00022:
00026:
00029: `define VMM_HW_RTL__SV
00030:
00031:
00032: //
00033: // Select the target architecture
00034: //
00035: `undef VMM_HW_ARCH
00036:
00044:
00045:
00047: // Throw a syntax error if more than one architecture was selected
00052: `define VMM_HW_ARCH
00054:
00055:
00056: // Throw a syntax error if no architecture was selected
00061:
00062:
00063: // Include the DUT if mapping to hardware platform (ie. synthesis)
00064: // or using the NULL architecture
00069: `define VMM_HW_INCL_DUT
00071:
00072:
00073: //
00074: //------------------------------------------------------------------
00075: //
00076:
00077:
00080: interface vmm_hw_in_if_itf(input logic rx_rdy,
00081: output logic tx_rdy,
00082: output logic [1024-1:0] msg,
00083: input logic uclk,
00084: input logic urst,
00085: input int width,
00086: input bit [1024*8-1:0] path);
00087:
00089: string inst = path;
00090: vmm_log log = new("vmm_hw_in_if", inst);
00091: bit in_use = 0;
00092:
00093: clocking ck @(posedge uclk);
00094: input rx_rdy;
00095: endclocking
00097:
00098: endinterface
00100:
00101:
00140:
00141:
00142: //
00143: //------------------------------------------------------------------
00144: //
00147: interface vmm_hw_out_if_itf(input logic tx_rdy,
00148: output logic rx_rdy,
00149: input logic [1024-1:0] msg,
00150: input logic uclk,
00151: input logic urst,
00152: input int width,
00153: input bit [1024*8-1:0] path);
00154:
00156: string inst = path;
00157: vmm_log log = new("vmm_hw_out_if", inst);
00158: bit in_use = 0;
00159:
00160: clocking ck @(posedge uclk);
00161: input tx_rdy;
00162: input msg;
00163: endclocking
00165:
00166:
00167: endinterface
00169:
00170:
00209:
00210:
00211:
00212: //
00213: //------------------------------------------------------------------
00214: //
00217: interface vmm_hw_clock_control_itf(input logic uclk,
00218: input logic urst,
00219: input logic rdy_for_cclk,
00220: output logic cclk_en,
00221: input logic rdy_for_cclk_neg,
00222: output logic cclk_neg_en,
00223: input bit [1024*8-1:0] path,
00224: input int clock_num);
00225:
00227: reg foo;
00229:
00230: endinterface
00232:
00233:
00284:
00285:
00286: //
00287: //------------------------------------------------------------------
00288: //
00344:
00345:
00346: //
00347: //------------------------------------------------------------------
00348: //
00351: interface vmm_hw_clock_itf(input int clock_num,
00352: input logic ck_en,
00353: input logic ckn_en,
00354: output int no_pos,
00355: output int no_neg);
00356: string controller[$];
00357: logic rdy_pos[$];
00358: logic rdy_neg[$];
00359:
00360: function void why();
00361: if (controller.size() == 0) begin
00362: $write("Clock source %M does not have any associated controllers\n");
00363: return;
00364: end
00365: $write("State of controllers associated with %M:\n");
00366: $write(" Pos Neg :: Instance\n");
00367: foreach(controller[i]) begin
00368: $write(" %b %b :: %s\n", rdy_pos[i], rdy_neg[i], controller[i]);
00369: end
00370: endfunction: why
00371:
00372: endinterface
00374:
00375:
00462: