00001 //
00002 // -------------------------------------------------------------
00003 // Copyright 2004-2008 Synopsys, Inc.
00004 // All Rights Reserved Worldwide
00005 //
00006 // Licensed under the Apache License, Version 2.0 (the
00007 // "License"); you may not use this file except in
00008 // compliance with the License. You may obtain a copy of
00009 // the License at
00010 //
00011 // http://www.apache.org/licenses/LICENSE-2.0
00012 //
00013 // Unless required by applicable law or agreed to in
00014 // writing, software distributed under the License is
00015 // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
00016 // CONDITIONS OF ANY KIND, either express or implied. See
00017 // the License for the specific language governing
00018 // permissions and limitations under the License.
00019 // -------------------------------------------------------------
00020 //
00021
00022
00023 `ifdef VMM_HW_XACTOR__SV
00024 `else
00025 `define VMM_HW_XACTOR__SV
00026
00027 typedef class vmm_hw_in_port;
00028 typedef class vmm_hw_out_port;
00029
00030 virtual class vmm_hw_arch;
00031 vmm_log log = new("vmm_hw_arch", "base class");
00032
00033 virtual function vmm_hw_in_port create_in_port(virtual vmm_hw_in_if_itf in_if,
00034 string name);
00035 `vmm_fatal(this.log, "vmm_hw_arch::create_in_port() not overloaded");
00036 return null;
00037 endfunction: create_in_port
00038
00039 virtual function vmm_hw_out_port create_out_port(virtual vmm_hw_out_if_itf out_if,
00040 string name);
00041 `vmm_fatal(this.log, "vmm_hw_arch::create_out_port() not overloaded");
00042 return null;
00043 endfunction: create_out_port
00044
00045 virtual function string connect_to(string hdl_path,
00046 string name);
00047 return hdl_path;
00048 endfunction: connect_to
00049
00050 virtual function void clk_control(virtual vmm_hw_clock_itf clk,
00051 virtual vmm_hw_clock_control_itf ctl);
00052 endfunction: clk_control
00053
00054 virtual function void init_sim();
00055 endfunction
00056
00057 endclass: vmm_hw_arch
00058
00059
00060 virtual class vmm_hw_in_port;
00061 vmm_log log = new("vmm_hw_in_port", "base class");
00062
00063 virtual function bit is_rdy();
00064 `vmm_fatal(this.log, "vmm_hw_in_port::is_rdy() not overloaded");
00065 endfunction: is_rdy
00066
00067 virtual task wait_is_rdy();
00068 `vmm_fatal(this.log, "vmm_hw_in_port::wait_is_rdy() not overloaded");
00069 endtask: wait_is_rdy
00070
00071 virtual task send(bit [`VMM_HW_DATA_WIDTH-1:0] data);
00072 `vmm_fatal(this.log, "vmm_hw_in_port::send() not overloaded");
00073 endtask: send
00074 endclass: vmm_hw_in_port
00075
00076
00077 virtual class vmm_hw_out_port;
00078 vmm_log log = new("vmm_hw_out_port", "base class");
00079
00080 virtual function bit is_rdy();
00081 `vmm_fatal(this.log, "vmm_hw_out_port::is_rdy() not overloaded");
00082 endfunction: is_rdy
00083
00084 virtual task wait_is_rdy();
00085 `vmm_fatal(this.log, "vmm_hw_out_port::wait_is_rdy() not overloaded");
00086 endtask: wait_is_rdy
00087
00088 virtual task receive(ref bit [`VMM_HW_DATA_WIDTH-1:0] data,
00089 ref time stamp);
00090 `vmm_fatal(this.log, "vmm_hw_out_port::receive() not overloaded");
00091 endtask: receive
00092 endclass: vmm_hw_out_port
00093
00094 `endif