Factory Input
-------------

It is required that you first set an input. Right-click on the element definition and select from the context menu the option :guilabel:`Set Factory Input` under :guilabel:`Code Factory`.

The current input persists until a new one is set or until a full build is invoked. 

.. note::

	The input can be either a SystemVerilog module, interface, program, checker or a VHDL entity.

Creating code
-------------

Having set an input, you can do one of the following:

-  **Create Instance** for instantiating the design element;  
-  **Create Signals** for listing the ports of the design element as signals;
-  **Create Testbench** for defining a testbench that instantiates the design element with all the required port connections already made;
-  **Create Component** for defining a component (VHDL only)
-  **Create WaveDrom Diagram** for defining a :ref:`WaveDrom Timing Diagrams` description stub
-  **Create from Custom Template**

The code will be inserted at the cursor's current position.

.. figure:: ../../images/common/code-factory-signals-output.png
	:align: center

  
Any information or errors during Code Factory operations are shown in the status bar.

.. figure:: ../../images/common/code-factory-status-bar.png
	:align: center


.. note::
	
	Cross language operations are not supported. You can't set a SystemVerilog module as input and use it in VHDL for creating output and vice-versa.
