Expand .* Port Connections
==========================


You can easily expand .* wildcard named port connections to explicit named port connections.

Place the editor cursor either on a module or interface instance declaration and press :kbd:`Ctrl+1`, select **Expand .* port connections** from the list of quick assist proposals and press  :kbd:`Enter`.

.. figure:: ../../images/common/sv_quick_assist_expand_dot_star_list.png



The .* connections are expanded to named port connections.

.. figure:: ../../images/common/sv_quick_assist_expand_dot_star_after.png

.. note::

	You can customize the look and feel of the explicit named port connections from **Window > Preferences > DVT > SystemVerilog > Editor > Content Assist**.

.. tip::

	You can also :kbd:`Right-Click` in the editor and go to **Refactor** > **Expand .* Port Connections**.

.. figure:: ../../images/common/sv_quick_assist_expand_dot_star_menu.png




