
An expression inside a function or task can be extracted to a local variable.

Select the expression and press :kbd:`Ctrl+1`, select **Extract to local variable** from the list of quick assist proposals and press  :kbd:`Enter`.

.. figure:: ../../images/common/sv_quick_assist_extract_to_variable_list.png


The variable is declared and initialized with the extracted expression in the correct scope.

.. figure:: ../../images/common/sv_quick_assist_extract_to_variable_after.png

.. note::

	By default, if and loop conditions are evaluated to the logic data type, according to the IEEE 1800-2023 Standard for SystemVerilog. You can enforce the data type to bit by going to :menuselection:`Window --> Preferences --> DVT --> SystemVerilog --> Refactoring` and enabling **Enforce condition data type to bit**.
	
	This preference applies only when you select the whole condition.


.. tip::

	You may change the variable name and type. **Press tab** to switch between the edit boxes.

.. tip::

	If the expression occurs multiple times throughout the function, you may chose to replace all the occurrences with the newly created variable, or only the selected one.

.. tip::

	You can also :kbd:`Right-Click` in the editor and go to **Refactor** > **Extract...**. 

.. figure:: ../../images/common/sv_quick_assist_extract_to_variable_menu.png

