.. _Icons and Decorations:

Icons and Decorations
=====================


Icons
~~~~~



.. list-table::
   :header-rows: 1
   :widths: auto

   * - .. figure:: ../../images/icons/obj16/vlog_file_obj.png
     - Regular Verilog/SystemVerilog File
   * - .. figure:: ../../images/icons/obj16/vlog_file_linked_obj.png
     - Linked Resource Verilog/SystemVerilog File   See :ref:`Linked Resources`.
   * - .. figure:: ../../images/icons/obj16/vlog_file_gray_obj.png
     - Out of Project Verilog/SystemVerilog File  The file is not inside a project directory, nor accessible as a linked resource. Functionality is limited on "gray" files.
   * - .. figure:: ../../images/icons/obj16/library_obj.png
     - Library
   * - .. figure:: ../../images/icons/obj16/package.png
     - Package
   * - .. figure:: ../../images/icons/obj16/program_obj.png
     - Program
   * - .. figure:: ../../images/icons/obj16/type_obj.png
     - Typedef
   * - .. figure:: ../../images/icons/obj16/class_obj.png
     - Class
   * - .. figure:: ../../images/icons/obj16/interface_obj.png
     - Interface
   * - .. figure:: ../../images/icons/obj16/module_obj.png
     - Module
   * - .. figure:: ../../images/icons/obj16/checker_obj.png
     - Checker
   * - .. figure:: ../../images/icons/obj16/primitive_obj.png
     - Primitive
   * - .. figure:: ../../images/icons/obj16/generate_obj.png
     - Generate
   * - .. figure:: ../../images/icons/obj16/field_obj.png
     - Field
   * - .. figure:: ../../images/icons/obj16/enum_item_obj.png
     - Enumeration name
   * - .. figure:: ../../images/icons/obj16/constructor_obj.png
     - Constructor
   * - .. figure:: ../../images/icons/obj16/method_obj.png
     - Function
   * - .. figure:: ../../images/icons/obj16/task_obj.png
     - Task
   * - .. figure:: ../../images/icons/obj16/event_obj.png
     - Event
   * - .. figure:: ../../images/icons/obj16/fork_join_obj.png
     - Fork/join - Indicates a fork block.
   * - .. figure:: ../../images/icons/obj16/fork_join_process_obj.png
     - Process - Indicates a process in a fork block.
   * - .. figure:: ../../images/icons/obj16/constraint_obj.png
     - Constraint
   * - .. figure:: ../../images/icons/obj16/coverage_obj.png
     - Cover Group
   * - .. figure:: ../../images/icons/obj16/in_port.png
     - Input Port
   * - .. figure:: ../../images/icons/obj16/out_port.png
     - Output Port
   * - .. figure:: ../../images/icons/obj16/inout_port.png
     - Bidirectional Port
   * - .. figure:: ../../images/icons/obj16/interface_port.png
     - Interface Port
   * - .. figure:: ../../images/icons/obj16/mod_port.png
     - ModPort
   * - .. figure:: ../../images/icons/obj16/multi_dir_port.png
     - Port passed multiple times when tracing a signal
   * - .. figure:: ../../images/icons/obj16/wire_obj.png
     - Wire
   * - .. figure:: ../../images/icons/obj16/trace_why_port_connection.png
     - Port connection
   * - .. figure:: ../../images/icons/obj16/always_obj.png
     - Always
   * - .. figure:: ../../images/icons/obj16/assign_obj.png
     - Assign
   * - .. figure:: ../../images/icons/obj16/module_instance_obj.png
     - Module Instance
   * - .. figure:: ../../images/icons/obj16/any_design_instance_warn_obj.png
     - Unknown Instance
   * - .. figure:: ../../images/icons/obj16/interface_instance_obj.png
     - Interface Instance
   * - .. figure:: ../../images/icons/obj16/class_instance_obj.png
     - Object Instance - Relevant for XVM methodologies, indicates a "created" object.
   * - .. figure:: ../../images/icons/obj16/xvm_component_instance_obj.png
     - Component Instance - Relevant for XVM methodologies, indicates a "created" component.
   * - .. figure:: ../../images/icons/obj16/xvm_test_obj.png
     - Test Class - Relevant for XVM methodologies, indicates a "test" class.
   * - .. figure:: ../../images/icons/obj16/sequence_obj.png
     - Sequence - Relevant for XVM methodologies, indicates a "sequence" class.
   * - .. figure:: ../../images/icons/obj16/sequence_item_obj.png
     - Sequence Item - Relevant for XVM methodologies, indicates a "sequence item" class.
   * - .. figure:: ../../images/icons/obj16/xvm_root_obj.png
     - Root Class - Relevant for XVM methodologies, indicates the "root" class.
   * - .. figure:: ../../images/icons/obj16/preproc_define.png
     - Preprocessing define
   * - .. figure:: ../../images/icons/obj16/preproc_undefine.png
     - Preprocessing undefine
   * - .. figure:: ../../images/icons/obj16/preproc_ifdef.png
     - Preprocessing ifdef, ifndef
   * - .. figure:: ../../images/icons/obj16/template_obj.png
     - Code Template For example in autocomplete proposals.


Decorations
~~~~~~~~~~~



Compiled Files
--------------



To enable/disable go to **Window > Preferences > General > Appearance > Label Decorations** preference page and check/uncheck **DVT Compiled File**.

.. list-table::
   :header-rows: 1
   :widths: auto

   * - .. figure:: ../../images/icons/ovr16/imported_file_ovr.png
     - Compiled File
   * - .. figure:: ../../images/icons/ovr16/ignored_imported_file_ovr.png
     - Skipped File


See also: :ref:`Build Configurations`.

Access Modifiers
----------------



To enable/disable go to **Window > Preferences > General > Appearance > Label Decorations** preference page and check/uncheck **Verilog Language Access Modifier**.

.. list-table::
   :header-rows: 1
   :widths: auto

   * - .. figure:: ../../images/icons/ovr16/private_ovr.png
     - Local
   * - .. figure:: ../../images/icons/ovr16/protected_ovr.png
     - Protected
   * - .. figure:: ../../images/icons/ovr16/public_ovr.png
     - Public


Errors and Warnings
-------------------



To enable/disable go to **Window > Preferences > General > Appearance > Label Decorations** preference page and check/uncheck **Verilog Language Problem**.

.. list-table::
   :header-rows: 1
   :widths: auto

   * - .. figure:: ../../images/icons/ovr16/error_co.png
     - Error
   * - .. figure:: ../../images/icons/ovr16/warning_co.png
     - Warning


Trace Connections
-----------------



.. list-table::
   :header-rows: 1
   :widths: auto

   * - .. figure:: ../../images/icons/ovr16/target_overlay_red.png
     - Signal source
   * - .. figure:: ../../images/icons/ovr16/target_overlay_green.png
     - Signal destination
   * - .. figure:: ../../images/icons/ovr16/target_overlay_mixed.png
     - Signal source and destination

.. _Changing Icon Colors:

Changing Icon Colors
~~~~~~~~~~~~~~~~~~~~

.. include:: icon-colors.rst

.. _Project Colors:

Project Colors
~~~~~~~~~~~~~~

.. include:: project-colors.rst