.. _Trace Connections from Design Hierarchy:

Trace Connections from Design Hierarchy
=======================================

.. |ports-icon| image:: ../../images/icons/act16/show_hide_ports.png
   :class: inline

.. rst-class:: lead

Start by inspecting the module hierarchy in the :ref:`Design Hierarchy View`. All traces are going to be computed on this design hierarchy.

You can trace across the whole design (when you pick a top module as the **hierarchy root**) or focus on a specific module in the design (when you pick that module as the **hierarchy root**). The :ref:`Design Hierarchy View` documentation provides more details on how to populate this view.

Select an instance and click on the |ports-icon| **Show/Hide Ports**  button in the toolbar.

Then *right click* on a port and select one of the trace kinds, for example :guilabel:`Trace Drive and Load`.

.. figure:: ../../images/common/design-hierarchy-trace-drive-and-load.png



The :ref:`Trace Connections View` opens.

.. note:: 

 Signals are traced across port connections and combinational logic: continuous assignments and combinational always blocks in SystemVerilog, concurrent signal assignments and combinational processes in VHDL.

.. note:: 

 Interface and struct type signals are supported.

