Elaboration is the process that occurs after the code is parsed. From one or more starting points, called tops, all instances have their designs computed, parameters and other constants get their values, generate constructs are instantiated and port connections are established.

In the project build config file, specify the elaboration top(s) with one or more -top top_name directives.

E.g.

work.elem_name - from the specified library, the SystemVerilog *module*, SystemVerilog *configuration*, VHDL *entity* or VHDL *configuration* is set as the top

elem_name - all libraries are searched for the design element and the first found is set as top

elem_name:config - the configuration specified is the top, even in the case of a name collision with either a SystemVerilog module or a VHDL entity

If no directive is used, then the elaboration is preceded by a top candidates search through all the designs. A UNSPECIFIED_TOP warning is also displayed in the Console View to mark the absence of any chosen top design.

Note

SystemVerilog modules can be instantiated by a VHDL entity and vice versa. You can also specify design tops from either language.

Top candidates

When no top design element is specified in the project build config file, then any design element that satisfies the following requirements is considered a top:

  1. The design element is either a SystemVerilog module, a SystemVerilog program, a VHDL entity or a VHDL configuration. Do note that a SystemVerilog configuration cannot be a candidate.

  2. The design element is not instantiated anywhere. Even instantiations under inactive generate constructs are considered and rule out the element in question.

  3. Customizable: The design element has sub-instances or local generate constructs. This requirement can be disabled by specifying in the project build config the following directive: +dvt_enable_elaboration_empty_tops+true.

As mentioned before, a mixed-language project can have any combination of SystemVerilog, SystemVerilog or VHDL top candidates.

Parameter values

During elaboration, parameters (or generics in VHDL) get their values computed. The following sources, ordered by importance, are searched:

  • Configuration overrides. Any override of a parameter in a SystemVerilog config or a VHDL configuration rule is considered first.

SystemVerilog
config cfg;


instance top.inst use amod #(.PARAM(1))


endconfig
VHDL
configuration cfg of top_entity

for rtl


  for inst : aent use entity work.aent
    generic map (PARAM => 1);
  end for;



end for;

end configuration;

  • Defparam assignments

SystemVerilog
defparam top.inst.PARAM = 1;

  • Instantiation overrides

SystemVerilog
amod #(.PARAM(1)) inst();
VHDL
inst : entity work.aent
      generic map (PARAM => 1);

  • Default values

SystemVerilog
parameter int PARAM = 1;
VHDL
generic (PARAM : integer := 1);