.. _Compatibility Modes:

Compatibility Modes
===================

.. rst-class:: lead

A compatibility mode defines how DVT decides what top files to parse and with what language syntax to parse them.

File Extension to Language Syntax Mapping
  File extensions can be mapped either to a specific language syntax or **skipped (that is they will not be parsed)**.

  Each mode has a default file extension to syntax mapping.

  You control the extensions mapping by using various directives, like for example ``+verilog2001ext`` in :ref:`vcs.vlogan Compatibility Mode`.

  The ``+dvt_ext_unmap_all`` directive clears the syntax mapping, including skipped. This means that all top files will be parsed using the **Language Syntax for Unmapped Extensions**. Note that the syntax for unmapped extensions can be **Skip**, for example in the :ref:`Default DVT Compatibility Mode`, as a result nothing will be compiled.


Language Syntax for Unmapped Extensions
  An unmapped top file will be parsed using this syntax or skipped, depending on the compatibility mode.
  Can be controlled by various directives, like for example ``+dvt_ext_unmapped_syntax+<syntax>`` in the :ref:`Default DVT Compatibility Mode` or ``+v2k`` in :ref:`vcs.vlogan Compatibility Mode`.

Language Syntax for Included Files
  Where relevant, for example for Verilog/SystemVerilog, the included files are parsed either with the same syntax as the including file, or as specified by the extension mapping. See also each compatibility mode documentation.

.. note::
  
  A compatibility mode might also introduce specific predefined API, like for example Verilog preprocessing macros.

List of Compatibility Modes
---------------------------

The following compatibility modes are supported:

-  :ref:`dvt <Default DVT Compatibility Mode>` - **This is the default mode.**
-  :ref:`vcs.vlogan <vcs.vlogan Compatibility Mode>`
-  :ref:`vcs.vhdlan <vcs.vhdlan Compatibility Mode>`
-  :ref:`ius.irun <ius.irun Compatibility Mode>`
-  :ref:`xcelium.xrun <xcelium.xrun Compatibility Mode>`
-  :ref:`questa.vlog <questa.vlog Compatibility Mode>`
-  :ref:`questa.vcom <questa.vcom Compatibility Mode>`
-  :ref:`questa.qrun <questa.qrun Compatibility Mode>`

How to Specify the Compatibility Mode
-------------------------------------

The ``+dvt_init+<mode>`` directive changes the compatibility mode, where **<mode>** can be any of the above modes.

A ``+dvt_init+<mode>`` directive:

#.  Resets the dvt builder to the mode specific default state.
#.  Clears all the previous directives (preprocessing defines, system variables, libraries, etc.).

You can see it as the equivalent of a new tool invocation.

You may specify any number of ``+dvt_init`` directives inside a build file.

The compatibility mode is enforced until the next ``+dvt_init`` directive.

.. _Default DVT Compatibility Mode:

Default DVT Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+dvt`` directive resets the builder to the dvt default state.


.. list-table:: File Extension to Language Syntax Mapping
   :header-rows: 0
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - Verilog 2001
     - .v, .vh
   * - System Verilog 1800-2012
     - .vp, .vs, .vsh, .v95, .v95p, .sv, .svh, .svp, .svi, .sva
   * - VHDL 1076-2008
     - .vhd, .vhdl
   * - e Language 1647-2011
     - .e
   * - PSS DSL
     - .pss
   * - C/C++
     - .c, .h, .cpp, .cc, .cxx
   * - Shared objects (C/C++ libraries)
     - .so, .a, .o

Language Syntax for Unmapped Extensions:
  Skip unmapped extensions.

Language Syntax for Included Files:
  Included files are parsed as specified by the extension mapping.

.. list-table:: Mode Specific Directives
   :widths: 30 70

   * -  Directive
     -  Description
   * -  +dvt_ext_map+<syntax>+<ext>
     -  Files with <ext> extension are parsed using the specified <syntax>. See the list below for more details regarding <syntax>.
   * -  +dvt_ext_unmap+<ext>
     -  Files with <ext> extension are parsed using the ``Language Syntax for Unmapped Extensions``.
   * -  +dvt_ext_unmapped_syntax+<syntax>
     -  Set the ``Language Syntax for Unmapped Extensions``. See the list below for more details regarding <syntax>.
   * -  +dvt_ext_unmap_all
     -  All files are parsed using the ``Language Syntax for Unmapped Extensions``.
   * -  | +dvt_ext_included+by_ext
        | +dvt_ext_included+by_parent
     -  | by_ext: The included files are parsed using the syntax as specified by directives, that is using by ext syntax (if explicit) or the syntax for unmapped extensions
        |
        | by_parent: Included files are parsed using the syntax that was used for parsing the including file

Specifying a <syntax>
^^^^^^^^^^^^^^^^^^^^^

To specify the <syntax> for the directives above, one should use any of the following strings, case-insensitive:


 1364-1995, Verilog_95

 1364-2001-noconfig, Verilog_2001_noconfig

 1364-2001, Verilog_2001

 1364-2005, Verilog_2005

 VAMS-2.3, Verilog_AMS_23

 1800-2005, SystemVerilog_2005

 1800-2009, SystemVerilog_2009

 1800-2012, SystemVerilog_2012, SystemVerilog

 1800-2023, SystemVerilog_2023

 SVAMS, SystemVerilog_AMS

 1647-2011, e_2011, e

 1076-1987, VHDL_87

 1076-1993, VHDL_93

 1076.1-1999, VHDL_AMS_99

 1076-2000, VHDL_2000

 1076-2002, VHDL_2002

 1076.1-2007, VHDL_AMS_2007

 1076-2008, VHDL_2008, VHDL
 
 PSS

 SKIP

The dot (.) for specifying <ext> is optional. For example ``+dvt_ext_map+verilog_1364_1995+.svh`` and ``+dvt_ext_map+verilog_1364_1995+svh`` are equivalent.

You can specify more extensions at once, for example ``+dvt_ext_map+verilog_1364_1995+.svh+svp``.

When several directives change the syntax of a specific <ext>, the last one wins.

Examples
^^^^^^^^

.. code-block:: 
    :caption: I want to parse **.c** and **.v** files as SystemVerilog
    :emphasize-text: +dvt_ext_map

    +dvt_init+dvt // By default .c are skipped and .v are parsed with Verilog 2001 syntax
    +dvt_ext_map+SystemVerilog_2012+.v+.c // Now .c and .v are parsed with SystemVerilog 2012

.. note:: 
  
  Every time you re-map an already mapped extension, DVT will warn you. For the example above, you get the following warnings:
  
  - .v was previously mapped to Verilog_2001
  - .c was previously mapped to Skip

.. code-block:: 
    :caption: I want the **.vp** files to be parsed with the **Language Syntax for Unmapped Extensions**
    :emphasize-text: +dvt_ext_unmap

    +dvt_init+dvt // By default .vp is parsed with SystemVerilog 2012.
    +dvt_ext_unmap+.vp // Because by default the unmapped extensions are skipped, .vp files will be skipped

.. code-block:: 
    :caption: I want to change the  **Language Syntax for Unmapped Extensions**
    :emphasize-text: +dvt_ext_unmapped_syntax

    +dvt_init+dvt // By default the unmapped extensions are skipped
    +dvt_ext_unmapped_syntax+Verilog_95 // Now unmapped extensions, for example .foo, will be parsed as Verilog 95

.. code-block:: 
    :caption: I want to configure everything from scratch
    :emphasize-text: +dvt_ext_map

    +dvt_init+dvt
    +dvt_ext_unmap_all // All files are skipped
    +dvt_ext_unmapped_syntax+Verilog_95 // Compile all files with unmapped extensions as Verilog 95
    +dvt_ext_map+skip+.cpp // Skip .cpp files
    +dvt_ext_map+SystemVerilog_95+.sv // Compile .sv as SystemVerilog
    +dvt_ext_map+VHDL_1076_1_1999+.vhd // Compile .vhd as VHDL-AMS

.. code-block:: 
    :caption: I want to parse everything as SystemVerilog

    +dvt_init+dvt
    +dvt_ext_unmap_all // All files are skipped
    +dvt_ext_unmapped_syntax+SystemVerilog  // All files are parsed as SystemVerilog

.. _gcc Compatibility Mode:

gcc Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+gcc`` directive resets the builder to the gcc default state.

.. list-table:: File Extension to Language Syntax Mapping
   :widths: 50 50

   * - Syntax
     - Extensions
   * - C/C++
     - .c, .i, .ii, .h, .cc, .cp, .cxx, .cpp, .CPP, .c++, .C, .hh, .H, .hp, .hxx, .hpp, .HPP, .h++, .tcc

Language Syntax for Unmapped Extensions:
  Skip unmapped extensions.

When you compile C/C++ code using gcc rather than the simulator, for each gcc invocation it is recommended to use a ``+dvt_init+gcc`` directive followed by the gcc command line arguments.

.. _ius.irun Compatibility Mode:

ius.irun Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+ius.irun`` directive resets the builder to the ius.irun default state.

.. list-table:: File Extension to Language Syntax Mapping

  * - Syntax
    - Extensions
  * - Verilog 1995
    - .v95, .v95p
  * - Verilog AMS 2.3
    - .vams
  * - Verilog 2001
    - .v, .vp, .vs
  * - System Verilog 1800-2012
    - .sv, .svp, .svi, .svh, .vlib, .vcfg
  * - System Verilog AMS
    - .svams
  * - VHDL 1987
    - .vhd, .vhdl, .vhdp, .vhdlp, .vhcfg
  * - VHDL AMS 1999
    - .vha, .vhams, .vhms
  * - VHDL 2008
    - .pslvhdl
  * - e Language 1647-2011
    - .e
  * - C/C++
    - .c, .h, .cc, .cpp, .cxx, .pslsc
  * - Shared objects (C/C++ libraries)
    - .o, .a, .so, .sl
  * - Skipped Files
    - .pslvlog, .s, .scs, .sp

Language Syntax for Unmapped Extensions:
  Skip
  
Language Syntax for Included Files:
  Included files are parsed using the syntax that was used for parsing the including file.

.. note::
  
  In IUS compatibility mode all directives are case-insensitive except for **-f** / **-F**.

.. note::
  
  In IUS compatibility mode, top and test files specified using relative paths are solved, in order, as relative to the compilation root, then **$SPECMAN_PATH** entries.

.. list-table:: Mode Specific Directives
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -ams
     -  All files that would be parsed with a Verilog / VHDL syntax flavor will be parsed with Verilog AMS 2.3 / VHDL AMS 1999 instead. Has precedence over other syntax specifications.
   * -  -amscompilefile *file:<file_path>[ ...]*
     -  Equivalent with specifying <file_path> as a top file.
   * -  -asext <ext>[,<ext>]
     -  Equivalent to ``-as_ext +<ext>[,<ext>]``
   * -  -ccext <ext>
     -  Equivalent to ``-c_ext +<ext>[,<ext>]``
   * -  -cxxext <ext>
     -  Equivalent to ``-cpp_ext +<ext>[,<ext>]``
   * -  -default_ext <syntax>
     -  Set the **Language Syntax for Unmapped Extensions**. See the list below for more details regarding the <syntax> argument.
   * -  -lps_1801 <upf_file>
     -  Specify a Unified Power Format file to be analyzed.
   * -  -lps_cpf <cpf_file>
     -  Specify a Common Power Format file to be analyzed.
   * -  | -makelib **<lib_name>**  ... -endlib
        |
        | -makelib /path/to/ **<lib_name>**  ... -endlib
        |
        | -makelib /some/path: **<lib_name>**  ... -endlib
        |
     -  | Compiles files specified inside a ``-makelib ... -endlib`` section into the **<lib_name>** library. 
        |
        | Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation.
        |
        | The ``-work`` directive is ignored within a makelib section.
   * -  -objext <ext>
     -  Equivalent to ``-o_ext +<ext>[,<ext>]``
   * -  | -ovm
        | -uvm
     -  | Load the OVM / UVM library from the IUS installation location.
        | 
        | For OVM: **`ncroot`/tools/methodology/OVM/CDNS-2.1.2** or **`ncroot`/tools/ovm** if the first does not exist.
        | 
        | For UVM: **`ncroot`/tools/methodology/UVM/CDNS-1.1d/sv** or **`ncroot`/tools/uvm/uvm_lib/uvm_sv** if the first does not exist.
        |

        .. note::
            If the path to OVM/UVM cannot be located within the IUS installation, the tool tries to load the library from ``$OVM_HOME`` or ``$DVT_OVM_HOME`` (resp. ``$UVM_HOME`` or ``$DVT_UVM_HOME``).
            If ``$DVT_OVM_HOME`` is not defined, it falls back to $DVT_HOME/predefined_projects/libs/ovm-2.1.2.
            If ``$DVT_UVM_HOME`` is not defined, it falls back to $DVT_HOME/predefined_projects/libs/uvm-1.2.
   * -  | -ovmhome <path>
        | -uvmhome <path>
     -  | If <path> is:
        | - ``the word "default"``: equivalent with -ovm / -uvm
        | - ``an existing absolute path or relative path``: load the OVM / UVM library from the specified <path>
        | - ``an existing subpath of `ncroot`/tools/methodology/OVM/``: load the OVM library from `ncroot`/tools/methodology/OVM/<path>
        | - ``an existing subpath of `ncroot`/tools/methodology/UVM/``: load the UVM library from `ncroot`/tools/methodology/UVM/<path>/sv. Has precedence over -ovm / -uvm.
   * -  -ml_uvm
     -  Load the UVM_ML library from the IUS installation location.
        For uvm: **`ncroot`/tools/methodology/UVM/CDNS-1.1d/ml**. 
        
        .. note::

          If the path to UVM_ML cannot be located within the IUS installation, the tool tries to load the library from ``$UVM_HOME`` or ``$DVT_UVM_HOME``.
   * -  -uvmexthome <path>
     -  If <path> is **an existing absolute path or relative path**: load the UVM extension files from the specified <path>.
        
        Should be used in conjunction with ``-uvmhome``.
   * -  -pkgsearch <lib>
     -  Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
   * -  -snpath <path>
     -  Equivalent to ``+dvt_setenv+SPECMAN_PATH=$SPECMAN_PATH:<path>``
   * -  -sndefine <arg>
     -  Equivalent to ``+define+<arg>``
   * -  -sv
     -  All files that would be parsed according to the ``File Extension to Language Syntax Mapping`` or ``Language Syntax for Unmapped Extensions`` with a Verilog syntax flavor will be parsed with SystemVerilog 2012 instead. Has precedence over ``-v1995``.
   * -  -svams_2019
     -  All Verilog/SystemVerilog files will be parsed with SystemVerilog AMS. Has precedence over other syntax specifications.
   * -  -<syntax>_ext [+]<ext>[,<ext>]
     -  | Files with <ext> extension will be parsed using the specified <syntax>. If the optional + is specified, the mapping will be added to the default ``File Extension to Language Syntax Mapping``. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default ``File Extension to Language Syntax Mapping`` will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - ''vlog_ext .svh,.svp''. The dot (.) for specifying <ext> is mandatory.
        |
        | The following directives are supported: -a_ext, -amsvhdl_ext, -amsvlog_ext, -as_ext, -c_ext, -cpp_ext, -dynlib_ext, -e_ext, -o_ext, -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext. See the list below for more details regarding <syntax>.
   * -  | -v1995
        | -v95
     -  All files that would be parsed according to the ``File Extension to Language Syntax Mapping`` or ``Language Syntax for Unmapped Extensions`` with Verilog 2001 will be parsed instead with a reduced keywordset variant of Verilog 2001. The reduced keywordset does not contain the keywords ``automatic``, ``localparam``, ``generate``, ``endgenerate``, and ``genvar``.
   * -  -v200x
     -  All files that would be parsed according to the ``File Extension to Language Syntax Mapping`` or ``Language Syntax for Unmapped Extensions`` with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 2008 instead. Has precedence over ``-v93``.
   * -  -v93
     -  All files that would be parsed according to the ``File Extension to Language Syntax Mapping`` or ``Language Syntax for Unmapped Extensions`` with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 93 instead.
   * -  -vhdlext <ext>
     -  Equivalent to ``-vhdl_ext +<ext>[,<ext>]``
   * -  -vlogext <ext>
     -  Equivalent to ``-vlog_ext +<ext>[,<ext>]``

.. list-table:: How to specify syntax directives
   :widths: 30 30 40

   * -  Language Syntax
     -  -default_ext <syntax>
     -  -<syntax>_ext
   * -  Verilog 2001
     -  -default_ext verilog
     -  -vlog_ext
   * -  Verilog 1995
     -  -default_ext verilog95
     -  N/A
   * -  SystemVerilog 2012
     -  -default_ext systemverilog, -default_ext vcnf
     -  -sysv_ext
   * -  VHDL 1987
     -  -default_ext vhdl, -default_ext vhcfg
     -  -vhdl_ext
   * -  e Language
     -  -default_ext e
     -  -e_ext
   * -  VHDL AMS 1999
     -  -default_ext vhdl-ams
     -  -amsvhdl_ext
   * -  SKIP
     -  | -default_ext verilog-ams, -default_ext psl_vlog,
        | -default_ext psl_vhdl, -default_ext psl_sc, -default_ext c,
        | -default_ext cpp, -default_ext assembly, -default_ext o,
        | -default_ext a, -default_ext so, -default_ext scs
     -  | -a_ext, -amsvhdl_ext, -amsvlog_ext,
        | -as_ext, -c_ext, -cpp_ext,
        | -dynlib_ext, -e_ext, -o_ext,
        | -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext

.. list-table:: Predefined API
   :header-rows: 0
   :widths: 30 70

   * - INCA
     - Defined as preprocessing macro without value.

Examples
^^^^^^^^

.. code-block:: 
    :caption:  I want to parse **.sv**, **.c** and **.v** files as SystemVerilog

    +dvt_init+ius.irun // By default .c are skipped and .v are parsed with Verilog 2001 syntax
    -sysv_ext +.v,.c // Now .c and .v are parsed with SystemVerilog 2012; however, the default extensions mapped to SystemVerilog 2012 still stand, including .sv

.. note:: 
  
  Every time you re-map an already mapped extension, DVT will warn you. For the example above, you get the following warnings:
  
  - **.v** was previously mapped to Verilog_2001
  - **.c** was previously mapped to Skip

.. code-block:: 
    :caption:  I want the **.vp** files to be parsed with the **Language Syntax for Unmapped Extensions**

    +dvt_init+ius.irun // By default .vp, .v, .vs are parsed with Verilog 2001
    -vlog_ext .v, .vs // We override the mapping for Verilog 2001 with only the other two extensions.
    // Now .vp is not mapped to any Language Syntax.
    // Because by default the unmapped extensions are skipped, .vp files will be skipped

.. code-block:: 
    :caption:   I want to change the  **Language Syntax for Unmapped Extensions**

    +dvt_init+ius.irun // By default the unmapped extensions are skipped
    -default_ext verilog95 // Now unmapped extensions, for example .foo, will be parsed as Verilog 95

.. code-block:: 
    :caption:   I want to parse all Verilog source files and all files with unmapped extensions as SystemVerilog, and all VHDL files as VHDL 2000

    +dvt_init+ius.irun
    -default_ext systemverilog // All files with unmapped extensions are parsed as SystemVerilog
    -sv // All Verilog source files are parsed with SystemVerilog
    -v200x // All VHDL source files are parsed with VHDL 2008

.. _ius.perspec Compatibility Mode:

ius.perspec Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+ius.perspec`` directive resets the builder to the ius.perspec default state.

.. list-table:: File Extension to Language Syntax Mapping
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - SLN
     - .sln
   * - PSS
     - .pss
   * - e Language 1647-2011
     - .e

Language Syntax for Unmapped Extensions:
  Skip unmapped extensions.

.. _questa.vcom Compatibility Mode:

questa.vcom Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+questa.vcom`` directive resets the builder to the questa.vcom default state.

Language Syntax for Unmapped Extensions:
  VHDL 1076-2002

.. list-table:: Mode Specific Directives
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -2002
     -  Enable support for VHDL 2002
   * -  -2008
     -  Enable support for VHDL 2008
   * -  -87
     -  Enable support for VHDL 87
   * -  -93
     -  Enable support for VHDL 93
   * -  -G <path/to/param>=<value>
     -  | Overrides the parameter at the given hierarchy path with 'value'.
        | Works similar to SystemVerilog defparam statement.
   * -  -pa_upf <upf_file>
     -  Specify a Unified Power Format file to be analyzed.

.. list-table:: Predefined API
   :header-rows: 0
   :widths: 30 70

   * -  QUESTA
     -  Defined as preprocessing macro without value.
   * -  MODEL_TECH
     -  Defined as preprocessing macro without value.

.. _questa.vlog Compatibility Mode:

questa.vlog Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


The ``+dvt_init+questa.vlog`` directive resets the builder to the questa.vlog default state.

.. list-table:: File Extension to Language Syntax Mapping
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - System Verilog 1800-2012
     - .sv, .svp, .svh
   * - C/C++
     - .c, .cpp, .cc, .cxx

Language Syntax for Unmapped Extensions:
  Verilog 1995

Language Syntax for Included Files:
  Included files are parsed using the syntax that was used for parsing the including file.

.. list-table:: Mode Specific Directives
   :header-rows: 0
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -G <path/to/param>=<value>
     -  | Overrides the parameter at the given hierarchy path with 'value'.
        | Works similar to SystemVerilog defparam statement, but has a higher priority and can also override localparams.
   * -  -ovm
     -  DVT tries to load the OVM library, in order of precedence from: ``$OVM_HOME``, ``$DVT_OVM_HOME``
   * -  -pa_upf <upf_file>
     -  Specify a Unified Power Format file to be analyzed.
   * -  -sv
     -  Parse files with unmapped extensions as SystemVerilog
   * -  -sv05compat
     -  Use SystemVerilog 2005 syntax flavor
   * -  -sv09compat
     -  Use SystemVerilog 2009 syntax flavor
   * -  -sv12compat
     -  Use SystemVerilog 2012 syntax flavor
   * -  -svfilesuffix=<ext1>[,<ext2>...]
     -  All files with <ext1>, <ext2>, ... extensions are parsed as SystemVerilog
   * -  -uvm
     -  | DVT compiles the UVM library, in order of precedence, from: ``$UVM_HOME``, ``$MTI_HOME/verilog_src/uvm-1.1d``, ``$DVT_UVM_HOME``, ``$DVT_HOME/predefined_projects/libs/uvm-1.2``
        | 
        | If ``$MTI_HOME`` is not defined, it is inferred from the location of the **vlog** executable
        |
        | If ``-L $MTI_HOME/<uvm_lib>`` is specified anywhere within the current invocation, then UVM is compiled from ``$MTI_HOME/verilog_src/<uvm_lib>``  
        |
        | Whenever compiling UVM from ``$MTI_HOME``, the $MTI_HOME/verilog_src/questa_uvm_pkg-1.2/ is also compiled
   * -  -vlog01compat
     -  USe Verilog 2001 syntax flavor
   * -  -vlog95compat
     -  Use Verilog 1995 syntax flavor

.. list-table:: Predefined API
   :header-rows: 0
   :widths: 30 70

   * -  QUESTA
     -  Defined as preprocessing macro without value.
   * -  MODEL_TECH
     -  Defined as preprocessing macro without value.


.. _questa.qrun Compatibility Mode:

questa.qrun Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


The ``+dvt_init+questa.qrun`` directive resets the builder to the questa.qrun default state.

.. list-table::
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - Verilog 1995
     - .v95, .v95p
   * - Verilog 2001
     - .v, .vp, .vs
   * - System Verilog 1800-2012
     - .sv, .svp, .svi, .svh, .vlib, .vcfg, .pslvlog
   * - VHDL 1987
     - .vhd, .vhdl, .vhdp, .vhdlp
   * - VHDL 2008
     - .pslvhdl, .vhcfg
   * - C/c++
     - .c, .h, .cc, .cpp, .cxx

Language Syntax for Unmapped Extensions:
  Skip

Language Syntax for Included Files:
  Included files are parsed using the syntax that was used for parsing the including file.

.. list-table:: Mode Specific Directives
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -2002
     -  Enable support for VHDL 2002
   * -  -2008
     -  Enable support for VHDL 2008
   * -  -87
     -  Enable support for VHDL 87
   * -  -93
     -  Enable support for VHDL 93
   * -  -cuname <compilation_unit_name>
     -  Compile under <compilation_unit_name> package; the directive is enforced until: 
         
        * another -cuname directive is encountered 
        * ``+dvt_init`` directive is encountered
        * end of default.build is encountered
   * -  -defaultHDLCompiler=<vlog/vcom>
     -  All files that would be parsed according to the **Language Syntax for Unmapped Extensions** will be parsed with Verilog 2001 if vlog option is selected or VHDL 87 for vcom option.
   * -  -defineall <DEFINE_NAME>=<replacement>
     -  Define a preprocessing symbol for SystemVerilog and C/C++. The replacement is optional. You may quote the replacement with ticks (') or quotes ("). If defined, environment variables are expanded.
   * -  -f <filename>
     -  Specify a <filename> containing command line arguments
   * -  | -makelib **<lib_name>**
        |
        | -makelib /path/to/ **<lib_name>**
        |
        | -makelib /some/path:**<lib_name>** 
        |
        | ... -endlib
     -  Compiles files specified inside a ``-makelib ... -endlib`` section into the **<lib_name>** library. Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation. The ``-work`` directive is ignored within a makelib section.
   * -  -pa_upf <upf_file>
     -  Specify a Unified Power Format file to be analyzed.
   * -  -reflib <lib>
     -  Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
   * -  -sv
     -  Parse files with unmapped extensions as SystemVerilog
   * -  -sv05compat
     -  Use SystemVerilog 2005 syntax flavor
   * -  -sv09compat
     -  Use SystemVerilog 2009 syntax flavor
   * -  -sv12compat
     -  Use SystemVerilog 2012 syntax flavor
   * -  -svfilesuffix=<ext1>[,<ext2>...]
     -  All files with <ext1>, <ext2>, ... extensions are parsed as SystemVerilog
   * -  -sysc <c/c++ source files and options> -end
     -  Add ``$SYSTEMC_HOME/src`` as C include dir. Falls back to ``$DVT_SYSTEMC_HOME`` if ``$SYSTEMC_HOME`` is not defined.
   * -  -top <design_unit>
     -  Specify a design top module or configuration name. You can specify multiple tops either by using the directive multiple times or by specifying multiple top names separated by the '+' character or a combination thereof.
   * -  -uvm
     -  | DVT compiles the UVM library, in order of precedence, from: ``$UVM_HOME``, ``$MTI_HOME/verilog_src/uvm-1.1d``, ``$DVT_UVM_HOME``, ``$DVT_HOME/predefined_projects/libs/uvm-1.2`` 
        |
        | If ``$MTI_HOME`` is not defined, it is inferred from the location of the **vlog** executable
        |
        | If ``-L $MTI_HOME/<uvm_lib>`` is specified anywhere within the current invocation, then UVM is compiled from ``$MTI_HOME/verilog_src/<uvm_lib>``
        |
        | Whenever compiling UVM from ``$MTI_HOME``, the $MTI_HOME/verilog_src/questa_uvm_pkg-1.2/ is also compiled
   * -  -uvmhome <path>
     -  | If <path> is:
        | **the word "default"**: equivalent with -uvm
        |
        | **an existing absolute path or relative path**: load the UVM library from the specified <path>
        |
        | Has precedence over -uvm.
   * -  -uvmexthome <path>
     -  | If <path> is **an existing absolute path or relative path**: load the UVM extension files from the specified <path>.
        |
        | Should be used in conjunction with **-uvmhome**.
   * -  -vlog01compat
     -  Use Verilog 2001 syntax flavor
   * -  -vlog95compat
     -  Use Verilog 1995 syntax flavor
   * -  -vlog.ext=[+]<ext>
     -  Files with <ext> extension will be parsed using the Verilog 2001 syntax flavor. If the optional + is specified, the mapping will be added to the default **File Extension to Language Syntax Mapping**. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default **File Extension to Language Syntax Mapping** will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - ''vlog.ext=+.svh,.svp''. The dot (.) for specifying <ext> is mandatory.
   * -  -vcom.ext=[+]<ext>
     -  Files with <ext> extension will be parsed using the VHDL 87 syntax flavor. If the optional + is specified, the mapping will be added to the default **File Extension to Language Syntax Mapping**. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default **File Extension to Language Syntax Mapping** will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - ''vcom.ext=+.svh,.svp''. The dot (.) for specifying <ext> is mandatory.
   * -  -work <lib>
     -  Compile into library <lib>.
   * -  +UVM_TESTNAME=<testname>
     -  The name of the UVM test which will be automatically created under uvm_root.

.. list-table:: Predefined API
   :header-rows: 0
   :widths: 30 70

   * -  QUESTA
     -  Defined as preprocessing macro without value.
   * -  MODEL_TECH
     -  Defined as preprocessing macro without value.


.. _vcs.vhdlan Compatibility Mode:

vcs.vhdlan Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+vcs.vhdlan`` directive resets the builder to the vcs.vhdlan default state.

.. list-table:: File Extension to Language Syntax Mapping
   :header-rows: 0
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - C/C++
     - .c, .h, .cpp, .cc, .cxx
   * - Shared objects (C/C++ libraries)
     - .so, .a, .o

Language Syntax for Unmapped Extensions:
  VHDL 1076-1993

.. list-table:: Mode Specific Directives
   :header-rows: 0
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -pvalue+<path.to.param>=<value>
     -  | Overrides the parameter at the given hierarchy path with 'value'.
        | Works similar to SystemVerilog defparam statement.
   * -  -upf <upf_file>
     -  Specify a Unified Power Format file to be analyzed.
   * -  -vhdl87
     -  Sets the syntax for unmapped extensions to VHDL 1076-1987
   * -  | -w <lib>
        | -work <lib>
     -  Compile intro library <lib>

.. _vcs.vlogan Compatibility Mode:

vcs.vlogan Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+vcs.vlogan`` directive resets the builder to the vcs.vlogan default state.

.. list-table:: File Extension to Language Syntax Mapping
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - C/C++
     - .c, .cpp, .cc, .cxx
   * - Shared objects (C/C++ libraries)
     - .so, .a, .o


Language Syntax for Unmapped Extensions:
  Verilog 1995

Language Syntax for Included Files:
  Included files are parsed using the syntax that was used for parsing the including file.

.. list-table:: Mode Specific Directives
   :header-rows: 0
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -extinclude
     -  The included files are parsed using the syntax as specified by directives, that is using by ext syntax (if explicit) or the syntax for unmapped extensions. It overrides the default behavior.
   * -  -liblist <lib1>[+<lib2>+...]
     -  Specify the library search order for Verilog packages.
   * -  -ntb_opts [ rvm / vmm ]
     - | If ``$VCS_HOME`` is defined, equivalent with:
       | 
       | +incdir+$VCS_HOME/etc/[ rvm / vmm ]
       | 
       | $VCS_HOME/etc/[ rvm / vmm ]/vmm.sv
       | 
       | If ``$VCS_HOME`` is not defined, equivalent with:
       | 
       | +incdir+$DVT_VMM_HOME/sv/
       | 
       | $DVT_VMM_HOME/sv/vmm.sv
       | 
       | If ``$DVT_VMM_HOME`` is not defined, falls back to ``$DVT_HOME/predefined_projects/libs/vmm-1.2.2b``
   * -  -ntb_opts [ uvm / uvm-1.0 / uvm-1.1 / uvm-1.2 / uvm-ieee-2020-2.0 ]
     -  Compiles or references the UVM library. See more details below.
   * -  -pvalue+<path.to.param>=<value>
     -  | Overrides the parameter at the given hierarchy path with 'value'.
        | Works similar to SystemVerilog defparam statement, but has a higher priority and can also override localparams.
   * -  -sverilog
     -  Sets the syntax for unmapped extensions to SystemVerilog. This directive has precedence over +v2k.
   * -  +systemverilogext+<ext>
     -  All files with <ext> extension are parsed using the SystemVerilog syntax.
   * -  -upf <upf_file>
     -  Specify a Unified Power Format file to be analyzed.
   * -  +v2k
     -  Sets the syntax for unmapped extensions to Verilog 2001.
   * -  +verilog1995ext+<ext>
     -  All files with <ext> extension are parsed using the Verilog 1995 syntax.
   * -  +verilog2001ext+<ext>
     -  All files with <ext> extension are parsed using the Verilog 2001 syntax.

The dot (.) for specifying <ext> is optional. For example *+verilog1995ext+.svh* and *+verilog1995ext+svh* are equivalent.

You can specify more extensions at once, for example *+verilog1995ext+.svh+svp*.

When several directives change the syntax of a specific <ext>, the last one wins.

**ntb_opts [ uvm / uvm-1.0 / uvm-1.1 / uvm-1.2 / uvm-ieee-2020-2.0 ]**

**Typical use-case #1 - single vcs command**

Command:


 vcs -ntb_opts uvm top1.sv top2.sv [other compilation directives]

Build config:

.. code-block::

 // The UVM library is compiled from $VCS_UVM_HOME or $VCS_HOME/etc/uvm or $DVT_UVM_HOME
 // (in this order of precedence, depending on which environment variables are defined).
 +dvt_init+vcs.vlogan -ntb_opts uvm top_file1.sv top_file2.sv [other compilation directives]

**Typical use-case #2 - multiple vlogan commands**

Commands:


 vlogan -ntb_opts uvm

 vlogan -ntb_opts uvm top1.sv top2.sv [other compilation directives]

 vlogan -ntb_opts uvm top3.sv top4.sv [other compilation directives]

Build config:

.. code-block::

    // The UVM library is compiled from $VCS_UVM_HOME or $VCS_HOME/etc/uvm or $DVT_UVM_HOME
    // (in this order of precedence, depending on which environment variables are defined).
    +dvt_init+vcs.vlogan -ntb_opts uvm

    // The UVM library is not recompiled. It is "referenced" by adding the relevant incdirs.
    +dvt_init+vcs.vlogan -ntb_opts uvm top1.sv top2.sv [other compilation directives]

    // The UVM library is not recompiled. It is "referenced" by adding the relevant incdirs.
    +dvt_init+vcs.vlogan -ntb_opts uvm top3.sv top4.sv [other compilation directives]


.. note::
  
  In the invocations which "references" the UVM library (rows 7-10 in the table below) - **ntb_opts uvm** is equivalent with:
  
  .. code-block::
    
    +incdir+<VCS>/wrap
    +incdir+<UVM>/src

  and any **`include uvm_pkg.sv** will solve to **<VCS>/wrap/uvm_pkg.sv** which contains the following code:

  .. code-block::

    `ifndef WRAP_UVM_PKG_SV
    `define WRAP_UVM_PKG_SV

    `include "uvm_macros.svh"

    import uvm_pkg::*;

    `endif

.. note::
  
  The second, third, ... **ntb_opts uvm** invocations without top files (rows 4-6 in the table below) will take into account the **dvt_disable_uvm_reuse** directive.

**Details**

The effect of this directive in a particular invocation depends on the following factors:

-  if it's the **first** invocation which specifies -ntb_opts uvm
-  if the invocation specifies source files to be compiled (**top files**) in addition to the -ntb_opts uvm flag
-  if **$VCS_UVM_HOME / $VCS_HOME** environment variables are set

.. list-table::

   * -  **#**
     -  **First**
     -  **Top files**
     -  **$VCS_UVM_HOME**
     -  **$VCS_HOME**
     -  **Equivalent incdir(s)**
     -  **Equivalent top file**
   * -  ``1``
     -  Y
     -  ---
     -  Y
     -  ---
     -  $VCS_UVM_HOME
     -  $VCS_UVM_HOME/uvm_pkg.sv
   * -  ``2``
     -  Y
     -  ---
     -  N
     -  Y
     -  $VCS_HOME/etc/uvm[ -version ]/src
     -  $VCS_HOME/etc/uvm[ -version ]/src/uvm_pkg.sv
   * -  ``3``
     -  Y
     -  ---
     -  N
     -  N
     -  $DVT_UVM_HOME/src
     -  $DVT_UVM_HOME/src/uvm_pkg.sv
   * -  ``4``
     -  N
     -  N
     -  Y
     -  ---
     -  $VCS_UVM_HOME
     -  $VCS_UVM_HOME/uvm_pkg.sv
   * -  ``5``
     -  N
     -  N
     -  N
     -  Y
     -  $VCS_HOME/etc/uvm[ -version ]/src
     -  $VCS_HOME/etc/uvm[ -version ]/src/uvm_pkg.sv
   * -  ``6``
     -  N
     -  N
     -  N
     -  N
     -  $DVT_UVM_HOME/src
     -  $DVT_UVM_HOME/src/uvm_pkg.sv
   * -  ``7``
     -  N
     -  Y
     -  Y
     -  Y
     -  | $VCS_HOME/etc/uvm/vcs/wrap
        | $VCS_UVM_HOME
     - 
   * -  ``8``
     -  N
     -  Y
     -  Y
     -  N
     -  | $DVT_HOME/predefined_projects/libs/uvm/vcs/wrap
        | $VCS_UVM_HOME
     -  
   * -  ``9``
     -  N
     -  Y
     -  N
     -  Y
     -  | $VCS_HOME/etc/uvm/vcs/wrap
        | $VCS_HOME/etc/uvm[ -version ]/src
     - 
   * -  ``10``
     -  N
     -  Y
     -  N
     -  N
     -  | $DVT_HOME/predefined_projects/libs/uvm/vcs/wrap
        | $DVT_UVM_HOME/src
     - 

.. note::
  
  If **$DVT_UVM_HOME** is not defined, falls back to **$DVT_HOME/predefined_projects/libs/uvm-1.2**.

.. list-table:: Predefined API
   :header-rows: 0
   :widths: 30 70

   * - VCS
     - Defined as preprocessing macro without value.

.. _xcelium.xrun Compatibility Mode:

xcelium.xrun Compatibility Mode
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The ``+dvt_init+xcelium.xrun`` directive resets the builder to the xcelium.xrun default state.

.. list-table:: File Extension to Language Syntax Mapping
   :header-rows: 0
   :widths: 30 70

   * - **Syntax**
     - **Extensions**
   * - Verilog 1995
     - .v95, .v95p
   * - Verilog AMS 2.3
     - .vams
   * - Verilog 2001
     - .v, .vp, .vs
   * - System Verilog 1800-2012
     - .sv, .svp, .svi, .svh, .vlib, .vcfg
   * - System Verilog AMS
     - .svams
   * - VHDL 1987
     - .vhd, .vhdl, .vhdp, .vhdlp, .vhcfg
   * - VHDL AMS 1999
     - .vha, .vhams, .vhms
   * - VHDL 2008
     - .pslvhdl
   * - e Language 1647-2011
     - .e
   * - C/c++
     - .c, .h, .cc, .cpp, .cxx, .pslsc
   * - Shared objects (C/C++ libraries)
     - .o, .a, .so, .sl
   * - Skipped Files
     - .pslvlog, .s, .scs, .sp

Language Syntax for Unmapped Extensions:
  Skip

Language Syntax for Included Files:
  Included files are parsed using the syntax that was used for parsing the including file.

.. note::
  
  In XCELIUM compatibility mode all directives are case-insensitive except for **-f** / **-F**.

.. note::
  
  In XCELIUM compatibility mode, top and test files specified using relative paths are solved, in order, as relative to the compilation root, then **$SPECMAN_PATH** entries.

.. list-table:: Mode Specific Directives
   :header-rows: 0
   :widths: 30 70

   * -  **Directive**
     -  **Description**
   * -  -ams
     -  All files that would be parsed with a Verilog / VHDL syntax flavor will be parsed with Verilog AMS 2.3 / VHDL AMS 1999 instead. Has precedence over other syntax specifications.
   * -  -amscompilefile "file:<file_path>[ ...]"
     -  Equivalent with specifying <file_path> as a top file.
   * -  -asext <ext>[,<ext>]
     -  Equivalent to ``-as_ext +<ext>[,<ext>]``
   * -  -ccext <ext>
     -  Equivalent to ``-c_ext +<ext>[,<ext>]``
   * -  -cxxext <ext>
     -  Equivalent to ``-cpp_ext +<ext>[,<ext>]``
   * -  -default_ext <syntax>
     -  Set the **Language Syntax for Unmapped Extensions**. See the list below for more details regarding the <syntax> argument.
   * -  -defparam <path.to.param>=<value> 
     -  | Overrides the parameter at the given hierarchy path with 'value'.
        | Works similar to SystemVerilog defparam statement, but has a higher priority and can also override localparams.
   * -  -lps_1801 <upf_file>
     -  Specify a Unified Power Format file to be analyzed.
   * -  -lps_cpf <cpf_file>
     -  Specify a Common Power Format file to be analyzed.
   * -  | -makelib **<lib_name>**  ... -endlib
        |
        | -makelib /path/to/ **<lib_name>**  ... -endlib
        |
        | -makelib /some/path:**<lib_name>**  ... -endlib
     -  Compiles files specified inside a ``-makelib ... -endlib`` section into the **<lib_name>** library. Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation. The ``-work`` directive is ignored within a makelib section.
   * -  -objext <ext>
     -  Equivalent to ``-o_ext +<ext>[,<ext>]``
   * -  -uvm
     -  | Load the UVM library from the XCELIUM installation location.
        |
        | For uvm: **`ncroot`/tools/methodology/UVM/CDNS-1.1d/sv** or **`ncroot`/tools/uvm/uvm_lib/uvm_sv** if the first does not exist.
        |  

        .. note::
            
          If the path to UVM cannot be located within the XCELIUM installation, the tool tries to load the library from  **$UVM_HOME** or **$DVT_UVM_HOME**. If **$DVT_UVM_HOME** is not defined, falls back to **$DVT_HOME/predefined_projects/libs/uvm-1.2**.
   * -  -uvmhome <path>
     -  | If <path> is: 
        | **the word "default"**: equivalent with -uvm
        |
        | **an existing absolute path or relative path**: load the UVM library from the specified <path> 
        |
        | **an existing subpath of `ncroot`/tools/methodology/UVM/**: load the UVM library from `ncroot`/tools/methodology/UVM/<path>/sv
        |
        | Has precedence over -uvm.
   * -  -ml_uvm
     -  | Load the UVM_ML library from the XCELIUM installation location.
        | For uvm: **`ncroot`/tools/methodology/UVM/CDNS-1.1d/ml**.
        |
        
        .. note::
          
          If the path to UVM_ML cannot be located within the XCELIUM installation, the tool tries to load the library from **$UVM_HOME** or **$DVT_UVM_HOME**.
   * -  -uvmexthome <path>
     -  | If <path> is **an existing absolute path or relative path**: load the UVM extension files from the specified <path>.
        |
        | Should be used in conjunction with **-uvmhome**.
   * -  -pkgsearch <lib>
     -  Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
   * -  -snpath <path>
     -  Equivalent to ``+dvt_setenv+SPECMAN_PATH=$SPECMAN_PATH:<path>``
   * -  -sndefine <arg>
     -  Equivalent to ``+define+<arg>``
   * -  -sv
     -  All files that would be parsed according to the **File Extension to Language Syntax Mapping** or **Language Syntax for Unmapped Extensions** with a Verilog syntax flavor will be parsed with SystemVerilog 2012 instead. Has precedence over ``-v1995``.
   * -  -svams_2019
     -  All Verilog/SystemVerilog files will be parsed with SystemVerilog AMS. Has precedence over other syntax specifications.
   * -  -<syntax>_ext [+]<ext>[,<ext>]
     -  | Files with <ext> extension will be parsed using the specified <syntax>. If the optional + is specified, the mapping will be added to the default **File Extension to Language Syntax Mapping**. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default **File Extension to Language Syntax Mapping** will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - ''vlog_ext .svh,.svp''. The dot (.) for specifying <ext> is mandatory.
        |
        | The following directives are supported: -a_ext, -amsvhdl_ext, -amsvlog_ext, -as_ext, -c_ext, -cpp_ext, -dynlib_ext, -e_ext, -o_ext, -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext. See the list below for more details regarding <syntax>.
   * -  | -v1995
        |
        | -v95
     -  All files that would be parsed according to the **File Extension to Language Syntax Mapping** or **Language Syntax for Unmapped Extensions** with Verilog 2001 will be parsed instead with a reduced keywordset variant of Verilog 2001. The reduced keywordset does not contain the keywords **automatic**, **localparam**, **generate**, **endgenerate**, and **genvar**.
   * -  -v200x
     -  All files that would be parsed according to the **File Extension to Language Syntax Mapping** or **Language Syntax for Unmapped Extensions** with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 2008 instead. Has precedence over -v93.
   * -  -v93
     -  All files that would be parsed according to the **File Extension to Language Syntax Mapping** or **Language Syntax for Unmapped Extensions** with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 93 instead.
   * -  -vhdlext <ext>
     -  Equivalent to ``-vhdl_ext +<ext>[,<ext>]``
   * -  -vlogext <ext>
     -  Equivalent to ``-vlog_ext +<ext>[,<ext>]``

How to specify <syntax> for - *default_ext <syntax>* and - *<syntax>_ext* directives
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

.. list-table::
   :widths: 30 30 40

   * - **Language Syntax**
     - **- default_ext <syntax>**
     - **- <syntax>_ext**
   * -  Verilog 2001
     -  -default_ext verilog
     -  -vlog_ext
   * -  Verilog 1995
     -  -default_ext verilog95
     -  N/A
   * -  SystemVerilog 2012
     -  -default_ext systemverilog, -default_ext vcnf
     -  -sysv_ext
   * -  VHDL 1987
     -  -default_ext vhdl, -default_ext vhcfg
     -  -vhdl_ext
   * -  e Language
     -  -default_ext e
     -  -e_ext
   * -  VHDL AMS 1999
     -  -default_ext vhdl-ams
     -  -amsvhdl_ext
   * -  SKIP
     -  | -default_ext verilog-ams, -default_ext psl_vlog,
        |
        | -default_ext psl_vhdl, -default_ext psl_sc, -default_ext c,
        |
        | -default_ext cpp, -default_ext assembly, -default_ext o,
        |
        | -default_ext a, -default_ext so, -default_ext scs
     -  | -a_ext, -amsvhdl_ext, -amsvlog_ext,
        |
        | -as_ext, -c_ext, -cpp_ext,
        |
        | -dynlib_ext, -e_ext, -o_ext,
        |
        | -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext

.. list-table:: Predefined API
   :header-rows: 0
   :widths: 30 70

   * - INCA
     - Defined as preprocessing macro without value.
   * - XCELIUM
     - Defined as preprocessing macro without value.

Examples
^^^^^^^^

.. code-block:: 
    :caption:  I want to parse **.sv**, **.c** and **.v** files as SystemVerilog:


    +dvt_init+xcelium.xrun // By default .c are skipped and .v are parsed with Verilog 2001 syntax
    -sysv_ext +.v,.c // Now .c and .v are parsed with SystemVerilog 2012; however, the default extensions mapped to SystemVerilog 2012 still stand, including .sv

.. note:: 
  
  Every time you re-map an already mapped extension, DVT will warn you. For the example above, you get the following warnings:

  - .v was previously mapped to Verilog_2001
  - .c was previously mapped to Skip

.. code-block:: 
    :caption:  I want the **.vp** files to be parsed with the **Language Syntax for Unmapped Extensions**

    +dvt_init+xcelium.xrun // By default .vp, .v, .vs are parsed with Verilog 2001
    -vlog_ext .v, .vs // We override the mapping for Verilog 2001 with only the other two extensions.
    // Now .vp is not mapped to any Language Syntax.
    // Because by default the unmapped extensions are skipped, .vp files will be skipped


.. code-block:: 
    :caption:  I want to change the  **Language Syntax for Unmapped Extensions**


    +dvt_init+xcelium.xrun // By default the unmapped extensions are skipped
    -default_ext verilog95 // Now unmapped extensions, for example .foo, will be parsed as Verilog 95


.. code-block:: 
    :caption: I want to parse all Verilog source files and all files with unmapped extensions as SystemVerilog, and all VHDL files as VHDL 2000

    +dvt_init+xcelium.xrun
    -default_ext systemverilog // All files with unmapped extensions are parsed as SystemVerilog
    -sv // All Verilog source files are parsed with SystemVerilog
    -v200x // All VHDL source files are parsed with VHDL 2008


