DVT IDE for VS Code SystemVerilog User Guide
Rev. 24.1.12, 12 June 2024

Chapter 19. Code Factory

The Code Factory allows you to easily generate instances, signals, and testbenches starting with modules or entities.

Factory Input

It is required that you first set an input. Place the cursor on a SystemVerilog module, interface, program, checker, or a VHDL entity definition and use the "DVT: Set Code Factory Input" command.

The current input persists until it is cleared ( "DVT: Clear Code Factory Input" command) or until a new one is set. Invoking a full build will also clear the current input.

Creating Code

Having set an input, you can use the "Trigger Suggest" command in order to do one of the following:

  • Create Instance for instantiating the design element

  • Create Signals for listing the ports of the design element as signals

  • Create Testbench for defining a testbench that instantiates the design element with all the required port connections already made

  • Create WaveDrom Diagram for defining a WaveDrom timing diagram description stub

  • Load Template for loading a custom FreeMarker Template and creating code based on it.

The code will be inserted at the cursor's current position.

Any information or errors during Code Factory operations are shown via notifications.

Load Template

You can customize the output of the Code Factory using FreeMarker Templates. API is available on the FreeMarker model root.

In the script template you can access structured data describing the design which has been set as factory input. The design is represented by the model root.

The following API is accessible in the FreeMarker template:

Design API

  • root.hasPorts()

  • root.getPorts(): returns a list of all the ports (see port API below)

  • root.hasParameters()

  • root.getParameters(): returns a list of all the parameters (see parameter API below)

Port API

  • port.getDirection()

  • port.getData(): returns the port data (see port data API below)

  • port.isInterfacePort()

  • port.isGenericInterfacePort()

  • port.getInterface(): returns the interface for interface ports

Port Data API

  • portData.getType()

  • portData.getNetType()

  • portData.hasPackedDimension()

  • portData.getPacketDimension()

  • portData.hasUnpackedDimension()

  • portData.getUnpackedDimension()

  • portData.hasSign()

  • portData.getSign()

Parameter API

  • parameter.getInitialValue()

  • parameter.hasInitialValue()

  • parameter.isLocal()


<#assign module = root>
<#assign max_port_name_chr = 0>
<#assign max_port_type_chr = 5>
<#--Determine the max length for ports -->
<#if module.hasPorts()>
<#list module.getPorts() as port>
<#assign port_name_chr = (port.getName())?length>
<#if max_port_name_chr < port_name_chr>
  <#assign max_port_name_chr = port_name_chr>
<#assign port_type_chr = (port.getData().getType())?length>
<#if max_port_type_chr < port_type_chr>
  <#assign max_port_type_chr = port_type_chr>
<#--print ports -->
<#if module.hasPorts()>
<#list module.getPorts() as port>
<#assign port_name = r"${" + port.getName() + "}">
<#assign pad = max_port_name_chr + 3>
<#assign data = port.getData()>
<#assign type = data.getType()?lower_case>
<#if !(type?has_content)>
<#assign type = "logic">
${type?right_pad(max_port_type_chr) + " " + port_name?right_pad(pad) + ";"}

Note: Cross language operations are not supported. You can't set a SystemVerilog module as input and use it in VHDL for creating output and vice-versa.