DVT IDE for VS Code SystemVerilog User Guide
Rev. 24.1.12, 12 June 2024

22.2.4 Finite-State Machine Diagrams

The "DVT: Show Diagram" command on a state variable inside a module or entity will generate a Finite-State Machine (FSM) diagram. States and transitions are automatically detected in the enclosing scope by analyzing all the assignments and conditions in which the state variable is used.

Multiple transitions between the same two states are merged into a single one with multiple conditions.

Next state variables are supported. Method call transitions and "one-hot" array case conditions are not supported.

The initial state is colored gray. Selecting any state or transition will highlight the previous and next states differently.

You can change the look and feel of the diagram using the preferences from the toolbar:

  • Graph Direction The direction of the diagram.

  • Placement Strategy The algorithm used for placing blocks and edges.

  • Opposite In/Out Edges for For which states should incoming and outgoing edges be constrained to opposite sides? The default is All States except Initial.

  • Initial State Position The position of the initial state relative to the graph direction. The default is First.

  • Show Explicit Loopback Edges Show explicit transitions to the same state as a loopback edge.

  • Transition Labels The label displayed on transitions. It can be the Index of the transition or the Condition (merged transitions will have multiple conditions). The default is None.

  • Hide Names in Conditions A list of signal names that will be filtered out of conditions. Strict text matching is used.

You can inspect transitions in the diagram table. Select any entry in the table and the transition will be highlighted in the diagram. Any selection in the diagram will highlight the corresponding elements in the table.

The conditions for all transitions are presented in the last column.