Verissimo SystemVerilog Testbench Linter User Guide
Rev. 24.2.25, 31 October 2024
| The +dvt_init+dvt directive resets the builder to the dvt default state. File Extension to Language Syntax Mapping
Language Syntax for Unmapped Extensions: Skip unmapped extensions. Language Syntax for Included Files: Included files are parsed as specified by the extension mapping. Mode Specific Directives
Specifying a <syntax> To specify the <syntax> for the directives above, one should use any of the following strings, case-insensitive: 1364-1995, Verilog_95 1364-2001-noconfig, Verilog_2001_noconfig 1364-2001, Verilog_2001 1364-2005, Verilog_2005 VAMS-2.3, Verilog_AMS_23 1800-2005, SystemVerilog_2005 1800-2009, SystemVerilog_2009 1800-2012, SystemVerilog_2012, SystemVerilog SVAMS, SystemVerilog_AMS 1647-2011, e_2011, e 1076-1987, VHDL_87 1076-1993, VHDL_93 1076.1-1999, VHDL_AMS_99 1076-2000, VHDL_2000 1076-2002, VHDL_2002 1076.1-2007, VHDL_AMS_2007 1076-2008, VHDL_2008, VHDL PSS SKIP The dot (.) for specifying <ext> is optional. For example +dvt_ext_map+verilog_1364_1995+.svh and +dvt_ext_map+verilog_1364_1995+svh are equivalent. You can specify more extensions at once, for example +dvt_ext_map+verilog_1364_1995+.svh+svp. When several directives change the syntax of a specific <ext>, the last one wins. Examples
+dvt_init+dvt // By default .c are skipped and .v are parsed with Verilog 2001 syntax Note Every time you re-map an already mapped extension, DVT will warn you. For the example above, you get the following warnings: .v was previously mapped to Verilog_2001
+dvt_init+dvt // By default .vp is parsed with SystemVerilog 2012.
+dvt_init+dvt // By default the unmapped extensions are skipped
+dvt_init+dvt
+dvt_init+dvt |