Verissimo SystemVerilog Testbench Linter User Guide
Rev. 24.1.12, 12 June 2024

8.3 Predefined Rulesets

Verissimo can be run either with a custom ruleset or one of the predefined rulesets. The available predefined rulesets are the following:

Ruleset Description Argument
All RulesAll the available rules from the rulepoolall
Basic RulesRules that are a good starting point in the absence of an existing guideline or custom rulesetbasic
UVM Compliance RulesRules related to UVM architecture compliance compliance
Dead Code RulesRules related to dead code detection: empty statements, unused elements, etc.dead_code
Non-Standard RulesRules responsible for detecting non-standard constructs or syntaxnon_standard
Performance RulesRules related to issues that can lead to poor simulator performanceperformance
RTL RulesRules related to RTL design issuesrtl
UVM IEEE 1800.2-2020 Compliance RulesRules that flag the usage of removed, deprecated, non-standard UVM IEEE API. This ruleset is useful in helping with migration to UVM IEEE.uvm_ieee

To run the predefined rulesets in batch mode simply use the associated argument (-all, -basic, etc) instead of -ruleset. By default if no -ruleset or no predefined ruleset argument is used, the Basic Rules will be run. In batch mode to generate the ruleset XML file use the -gen_ruleset_xml argument with the corresponding predefined ruleset argument: -gen_ruleset_xml -basic

For the associated HTML documentation of a predefined ruleset use the -gen_ruleset_doc argument: -gen_ruleset_doc -performance

To generate these file from DVT go to the Verissimo menu and go to Generate Doc... or Generate XML and select de desired ruleset.