Entity cache_cpu

Block Diagram of cache_cpu

Generics

Name	Type	Default	Description
REPLACEMENT_POLICY	string	"LRU"
CACHE_LINES	positive
ASSOCIATIVITY	positive
CPU_DATA_BITS	positive
MEM_ADDR_BITS	positive
MEM_DATA_BITS	positive

Ports

Name	Type	Direction	Description
clk	std_logic	in	clock
rst	std_logic	in	reset
cpu_req	std_logic	in	"CPU" side
cpu_write	std_logic	in
cpu_addr	unsigned	in
cpu_wdata	std_logic_vector	in
cpu_wmask	std_logic_vector	in
cpu_got	std_logic	out
cpu_rdata	std_logic_vector	out
mem_req	std_logic	out	Memory side
mem_write	std_logic	out
mem_addr	unsigned	out
mem_wdata	std_logic_vector	out
mem_wmask	std_logic_vector	out
mem_rdy	std_logic	in
mem_rstb	std_logic	in
mem_rdata	std_logic_vector	in

• Architecture rtl of cache_cpu
  • Processes

×