Entity cache_tagunit_par

Block Diagram of cache_tagunit_par

Tag-unit with fully-parallel compare of tag.

Configuration

Parameter	Description
REPLACEMENT_POLICY	Replacement policy. For supported policies see PoC.cache_replacement_policy.
CACHE_LINES	Number of cache lines.
ASSOCIATIVITY	Associativity of the cache.
ADDRESS_BITS	Number of address bits. Each address identifies exactly one cache line in memory.

Command truth table

Request	ReadWrite	Invalidate	Replace	Command
0	0	0	0	None
1	0	0	0	Read cache line
1	1	0	0	Update cache line
1	0	1	0	Read cache line and discard it
1	1	1	0	Write cache line and discard it
0		0	1	Replace cache line.

Operation

All inputs are synchronous to the rising-edge of the clock clock.

All commands use Address to lookup (request) or replace a cache line. Each command is completed within one clock cycle.

Upon requests, the outputs CacheMiss and CacheHit indicate (high-active) immediately (combinational) whether the Address is stored within the cache, or not. But, the cache-line usage is updated at the rising-edge of the clock. If hit, LineIndex specifies the cache line where to find the content.

The output ReplaceLineIndex indicates which cache line will be replaced as next by a replace command. The output OldAddress specifies the old tag stored at this index. The replace command will store the Address and update the cache-line usage at the rising-edge of the clock.

For a direct-mapped cache, the number of CACHE_LINES must be a power of 2. For a set-associative cache, the expression CACHE_LINES / ASSOCIATIVITY must be a power of 2.

Note

The port NewAddress has been removed. Use Address instead as described above.

If Address is fed from a register and an Altera FPGA is used, then Quartus Map converts the tag memory from a memory with asynchronous read to a memory with synchronous read by adding a pass-through logic. Quartus Map reports warning 276020 which is intended.

Warning

If the design is synthesized with Xilinx ISE / XST, then the synthesis option "Keep Hierarchy" must be set to SOFT or TRUE.

Generics

Name	Type	Default	Description
REPLACEMENT_POLICY	string	"LRU"
CACHE_LINES	positive	32
ASSOCIATIVITY	positive	32
ADDRESS_BITS	positive	8

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
Replace	std_logic	in
ReplaceLineIndex	std_logic_vector	out
OldAddress	std_logic_vector	out
Request	std_logic	in
ReadWrite	std_logic	in
Invalidate	std_logic	in
Address	std_logic_vector	in
LineIndex	std_logic_vector	out
TagHit	std_logic	out
TagMiss	std_logic	out

• Architecture rtl of cache_tagunit_par
  • Functions

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