Architecture rtl of cache_tagunit_seq

Processes

process @ ( NewTagSeqCounter_us or Replace or Replace_State or )

FSM Transitions for Replace_State

#	Current State	Next State	Condition
1	ST_IDLE	ST_REPLACE	[(Replace = '1')]
2	ST_REPLACE	ST_IDLE	[(NewTagSeqCounter_us = ite(TAG_BYTE_ORDER = LITTLE_ENDIAN, FA_CHUNKS - 1, 0))]

process @ ( TagHits_nor or TagSeqCounter_us or Request or Request_State or )

FSM Transitions for Request_State

#	Current State	Next State	Condition
1	ST_IDLE	ST_COMPARE	[((Request = '1') and not (TagHits_nor = '1'))]
2	ST_COMPARE	ST_IDLE	[(TagHits_nor = '1')]
3	ST_COMPARE	ST_READ	[(not (TagHits_nor = '1') and (TagSeqCounter_us = ite(TAG_BYTE_ORDER = LITTLE_ENDIAN, FA_CHUNKS - 1, 0)))]
4	ST_READ	ST_IDLE	[((Request = '1') and (TagHits_nor = '1'))]
5	ST_READ	ST_COMPARE	[((Request = '1') and not (TagHits_nor = '1'))]

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