Entity ddr2_mem2mig_adapter_Spartan6

Block Diagram of ddr2_mem2mig_adapter_Spartan6

Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to have multiple ports. One instance of this adapter is required for every port. The control signals for one port of the MIG IP core are prefixed by "cX_pY", meaning port Y on controller X.

Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found here.

Generic parameters:

• D_BITS: Data bus width of the PoC.Mem and MIG / MCBinterface. Also size of one word in bits.

• MEM_A_BITS: Address bus width of the PoC.Mem interface.

• APP_A_BTIS: Address bus width of the MIG / MCB interface.

Containts only combinational logic.

Generics

Name	Type	Default	Description
D_BITS	positive
MEM_A_BITS	positive
APP_A_BITS	positive

Ports

Name	Type	Direction	Description
mem_req	std_logic	in	PoC.Mem interface
mem_write	std_logic	in
mem_addr	unsigned	in
mem_wdata	std_logic_vector	in
mem_wmask	std_logic_vector	in
mem_rdy	std_logic	out
mem_rstb	std_logic	out
mem_rdata	std_logic_vector	out
mig_calib_done	std_logic	in	Xilinx MIG IP Core interface
mig_cmd_full	std_logic	in
mig_wr_full	std_logic	in
mig_rd_empty	std_logic	in
mig_rd_data	std_logic_vector	in
mig_cmd_instr	std_logic_vector	out
mig_cmd_en	std_logic	out
mig_cmd_bl	std_logic_vector	out
mig_cmd_byte_addr	std_logic_vector	out
mig_wr_data	std_logic_vector	out
mig_wr_mask	std_logic_vector	out
mig_wr_en	std_logic	out
mig_rd_en	std_logic	out

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