Entity ddr3_mem2mig_adapter_Series7

Block Diagram of ddr3_mem2mig_adapter_Series7

Simplifies the application interface ("app") of the Xilinx MIG IP core. The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found here.

Generic parameters:

• D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one word in bits.

• DQ_BITS: Size of data bus between memory controller and external memory (DIMM, SoDIMM).

• MEM_A_BITS: Address bus width of the PoC.Mem interface.

• APP_A_BTIS: Address bus width of the "app" interface.

Containts only combinational logic.

Generics

Name	Type	Default	Description
D_BITS	positive
DQ_BITS	positive
MEM_A_BITS	positive
APP_A_BITS	positive

Ports

Name	Type	Direction	Description
mem_req	std_logic	in	PoC.Mem interface
mem_write	std_logic	in
mem_addr	unsigned	in
mem_wdata	std_logic_vector	in
mem_wmask	std_logic_vector	in
mem_rdy	std_logic	out
mem_rstb	std_logic	out
mem_rdata	std_logic_vector	out
init_calib_complete	std_logic	in	Xilinx MIG IP Core interface
app_rd_data	std_logic_vector	in
app_rd_data_end	std_logic	in
app_rd_data_valid	std_logic	in
app_rdy	std_logic	in
app_wdf_rdy	std_logic	in
app_addr	std_logic_vector	out
app_cmd	std_logic_vector	out
app_en	std_logic	out
app_wdf_data	std_logic_vector	out
app_wdf_end	std_logic	out
app_wdf_mask	std_logic_vector	out
app_wdf_wren	std_logic	out

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