[source]

Component ddrio_inout_xilinx

BITSClockOutstd_logicClockOutEnablestd_logicOutputEnablestd_logicDataOut_high[BITS - 1 downto 0]std_logic_vectorDataOut_low[BITS - 1 downto 0]std_logic_vectorClockInstd_logicClockInEnablestd_logicDataIn_highstd_logic_vector[BITS - 1 downto 0]DataIn_lowstd_logic_vector[BITS - 1 downto 0]Padstd_logic_vector[BITS - 1 downto 0]

Block Diagram of ddrio_inout_xilinx

Generics

Name

Type

Initial Value

Description

BITS

positive

Ports

Name

Direction

Type

Description

ClockOut

in

std_logic

ClockOutEnable

in

std_logic

OutputEnable

in

std_logic

DataOut_high

in

std_logic_vector

DataOut_low

in

std_logic_vector

ClockIn

in

std_logic

ClockInEnable

in

std_logic

DataIn_high

out

std_logic_vector

DataIn_low

out

std_logic_vector

Pad

inout

std_logic_vector