[source]

Component ddrio_out_xilinx

NO_OUTPUT_ENABLEBITSINIT_VALUEClockstd_logicClockEnablestd_logicOutputEnablestd_logicDataOut_high[BITS - 1 downto 0]std_logic_vectorDataOut_low[BITS - 1 downto 0]std_logic_vectorPadstd_logic_vector[BITS - 1 downto 0]

Block Diagram of ddrio_out_xilinx

Generics

Name

Type

Initial Value

Description

NO_OUTPUT_ENABLE

boolean

false

BITS

positive

INIT_VALUE

bit_vector

x"FFFFFFFF"

Ports

Name

Direction

Type

Description

Clock

in

std_logic

ClockEnable

in

std_logic

OutputEnable

in

std_logic

DataOut_high

in

std_logic_vector

DataOut_low

in

std_logic_vector

Pad

out

std_logic_vector