Entity ddrio_in

Block Diagram of ddrio_in

Instantiates chip-specific DDR input registers.

Both data DataIn_high/low are synchronously outputted to the on-chip logic with the rising edge of Clock. DataIn_high is the value at the Pad sampled with the same rising edge. DataIn_low is the value sampled with the falling edge directly before this rising edge. Thus sampling starts with the falling edge of the clock as depicted in the following waveform.

After power-up, the output ports DataIn_high and DataIn_low both equal INIT_VALUE.

Pad must be connected to a PAD because FPGAs only have these registers in IOBs.

Generics

Name	Type	Default	Description
BITS	positive
INIT_VALUE	bit_vector	x"FFFFFFFF"

Ports

Name	Type	Direction	Description
Clock	std_logic	in
ClockEnable	std_logic	in
DataIn_high	std_logic_vector	out
DataIn_low	std_logic_vector	out
Pad	std_logic_vector	in

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