[source]

Entity ddrio_inout_altera

BITSClockOutstd_logicClockOutEnablestd_logicOutputEnablestd_logicDataOut_high[BITS - 1 downto 0]std_logic_vectorDataOut_low[BITS - 1 downto 0]std_logic_vectorClockInstd_logicClockInEnablestd_logicDataIn_highstd_logic_vector[BITS - 1 downto 0]DataIn_lowstd_logic_vector[BITS - 1 downto 0]Padstd_logic_vector[BITS - 1 downto 0]

Block Diagram of ddrio_inout_altera

See PoC.io.ddrio.inout for interface description.

Generics

Name

Type

Default

Description

BITS

positive

Ports

Name

Type

Direction

Description

ClockOut

std_logic

in

ClockOutEnable

std_logic

in

OutputEnable

std_logic

in

DataOut_high

std_logic_vector

in

DataOut_low

std_logic_vector

in

ClockIn

std_logic

in

ClockInEnable

std_logic

in

DataIn_high

std_logic_vector

out

DataIn_low

std_logic_vector

out

Pad

std_logic_vector

inout