Entity ddrio_out

Block Diagram of ddrio_out

Instantiates chip-specific DDR output registers.

Both data DataOut_high/low as well as OutputEnable are sampled with the rising_edge(Clock) from the on-chip logic. DataOut_high is brought out with this rising edge. DataOut_low is brought out with the falling edge.

OutputEnable (Tri-State) is high-active. It is automatically inverted if necessary. If an output enable is not required, you may save some logic by setting NO_OUTPUT_ENABLE = true.

If NO_OUTPUT_ENABLE = false then output is disabled after power-up. If NO_OUTPUT_ENABLE = true then output after power-up equals INIT_VALUE.

Pad must be connected to a PAD because FPGAs only have these registers in IOBs.

Generics

Name	Type	Default	Description
NO_OUTPUT_ENABLE	boolean	false
BITS	positive
INIT_VALUE	bit_vector	x"FFFFFFFF"

Ports

Name	Type	Direction	Description
Clock	std_logic	in
ClockEnable	std_logic	in
OutputEnable	std_logic	in
DataOut_high	std_logic_vector	in
DataOut_low	std_logic_vector	in
Pad	std_logic_vector	out

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