[source]

Component fifo_dc_got_sm

D_BITSMIN_DEPTHclk_wrstd_logicrst_wrstd_logicputstd_logicdin[D_BITS - 1 downto 0]std_logic_vectorclk_rdstd_logicrst_rdstd_logicgotstd_logicfullstd_logicvalidstd_logicdoutstd_logic_vector[D_BITS - 1 downto 0]

Block Diagram of fifo_dc_got_sm

Generics

Name

Type

Initial Value

Description

D_BITS

positive

MIN_DEPTH

positive

Ports

Name

Direction

Type

Description

clk_wr

in

std_logic

rst_wr

in

std_logic

put

in

std_logic

din

in

std_logic_vector

full

out

std_logic

clk_rd

in

std_logic

rst_rd

in

std_logic

got

in

std_logic

valid

out

std_logic

dout

out

std_logic_vector