[source]

Entity fifo_glue

D_BITSclkstd_logicrststd_logicputstd_logicdi[D_BITS - 1 downto 0]std_logic_vectorgotstd_logicfulstd_logicvldstd_logicdostd_logic_vector[D_BITS - 1 downto 0]

Block Diagram of fifo_glue

Its primary use is the decoupling of enable domains in a processing pipeline. Data storage is limited to two words only so as to allow both the ful and the vld indicators to be driven by registers.

Generics

Name

Type

Default

Description

D_BITS

positive

Data Width

Ports

Name

Type

Direction

Description

clk

std_logic

in

Control Clock

rst

std_logic

in

Synchronous Reset

put

std_logic

in

Input Put Value

di

std_logic_vector

in

Data Input

ful

std_logic

out

Full

vld

std_logic

out

Output Data Available

do

std_logic_vector

out

Data Output

got

std_logic

in

Data Consumed