Entity fifo_ic_got

Block Diagram of fifo_ic_got

Independent clocks meens that read and write clock are unrelated.

This implementation uses dedicated block RAM for storing data.

First-word-fall-through (FWFT) mode is implemented, so data can be read out as soon as valid goes high. After the data has been captured, then the signal got must be asserted.

Synchronous reset is used. Both resets may overlap.

DATA_REG (=true) is a hint, that distributed memory or registers should be used as data storage. The actual memory type depends on the device architecture. See implementation for details.

*STATE_*_BITS defines the granularity of the fill state indicator *state_*. fstate_rd is associated with the read clock domain and outputs the guaranteed number of words available in the FIFO. estate_wr is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the full or valid outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state.

If a fill state is not of interest, set *STATE_*_BITS = 0.

fstate_rd and estate_wr are combinatorial outputs and include an address comparator (subtractor) in their path.

Examples: - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full

fstate_rd == 1 => 1/2 full (half full)

• FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full

  fstate_rd == 1 => 1/4 full fstate_rd == 2 => 2/4 full fstate_rd == 3 => 3/4 full

Generics

Name	Type	Default	Description
D_BITS	positive		Data Width
MIN_DEPTH	positive		Minimum FIFO Depth
DATA_REG	boolean	false	Store Data Content in Registers
OUTPUT_REG	boolean	false	Registered FIFO Output
ESTATE_WR_BITS	natural	0	Empty State Bits
FSTATE_RD_BITS	natural	0	Full State Bits

Ports

Name	Type	Direction	Description
clk_wr	std_logic	in	Write Interface
rst_wr	std_logic	in
put	std_logic	in
din	std_logic_vector	in
full	std_logic	out
estate_wr	std_logic_vector	out
clk_rd	std_logic	in	Read Interface
rst_rd	std_logic	in
got	std_logic	in
valid	std_logic	out
dout	std_logic_vector	out
fstate_rd	std_logic_vector	out

• Architecture rtl of fifo_ic_got
  • Processes

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