Entity fifo_shift

Block Diagram of fifo_shift

This FIFO implementation is based on an internal shift register. This is especially useful for smaller FIFO sizes, which can be implemented in LUT storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is maintained, which determines the number of valid entries within the underlying shift register.

The specified depth (MIN_DEPTH) is rounded up to the next suitable value.

Generics

Name	Type	Default	Description
D_BITS	positive		Data Width
MIN_DEPTH	positive		Minimum FIFO Size in Words

Ports

Name	Type	Direction	Description
clk	std_logic	in	Global Control
rst	std_logic	in
put	std_logic	in	Writing Interface Write Request
din	std_logic_vector	in	Input Data
ful	std_logic	out	Capacity Exhausted
got	std_logic	in	Reading Interface Read Done Strobe
dout	std_logic_vector	out	Output Data
vld	std_logic	out	Data Valid

• Architecture rtl of fifo_shift

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