Entity io_PulseWidthModulation

Block Diagram of io_PulseWidthModulation

This module generates a pulse width modulated signal, that can be configured in frequency (PWM_FREQ) and modulation granularity (PWM_RESOLUTION).

Generics

Name	Type	Default	Description
CLOCK_FREQ	FREQ	100 MHz
PWM_FREQ	FREQ	1 kHz
PWM_RESOLUTION	positive	8

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
PWMIn	std_logic_vector	in
PWMOut	std_logic	out

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