[source]

Entity lut_Sine

REG_OUTPUTMAX_AMPLITUDEPOINTSOFFSET_DEGQUARTERSClockstd_logicInput[log2ceilnz ( POINTS ) - 1 downto 0]std_logic_vectorOutputstd_logic_vector[log2ceilnz ( MAX_AMPLITUDE + ( ( QUARTERS - 1 ) / 2 ) ) downto 0]

Block Diagram of lut_Sine

Generics

Name

Type

Default

Description

REG_OUTPUT

boolean

TRUE

MAX_AMPLITUDE

positive

255

POINTS

positive

4096

OFFSET_DEG

REAL

0.0

QUARTERS

positive

4

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Input

std_logic_vector

in

Output

std_logic_vector

out