[source]

Entity mac_RX_DestMAC_Switch

DEBUGMAC_ADDRESSESMAC_ADDRESSE_MASKSClockstd_logicResetstd_logicIn_Validstd_logicIn_DataT_SLV_8In_SOFstd_logicIn_EOFstd_logicOut_Ack[MAC_ADDRESSES ' length - 1 downto 0]std_logic_vectorOut_Meta_DestMACAddress_rst[MAC_ADDRESSES ' length - 1 downto 0]std_logic_vectorOut_Meta_DestMACAddress_nxt[MAC_ADDRESSES ' length - 1 downto 0]std_logic_vectorIn_Ackstd_logicOut_Validstd_logic_vector[MAC_ADDRESSES ' length - 1 downto 0]Out_DataT_SLVV_8[MAC_ADDRESSES ' length - 1 downto 0]Out_SOFstd_logic_vector[MAC_ADDRESSES ' length - 1 downto 0]Out_EOFstd_logic_vector[MAC_ADDRESSES ' length - 1 downto 0]Out_Meta_DestMACAddress_DataT_SLVV_8[MAC_ADDRESSES ' length - 1 downto 0]

Block Diagram of mac_RX_DestMAC_Switch

Generics

Name

Type

Default

Description

DEBUG

boolean

FALSE

MAC_ADDRESSES

T_NET_MAC_ADDRESS_VECTOR

(0 => C_NET_MAC_ADDRESS_EMPTY)

MAC_ADDRESSE_MASKS

T_NET_MAC_ADDRESS_VECTOR

(0 => C_NET_MAC_MASK_DEFAULT)

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

In_Valid

std_logic

in

In_Data

T_SLV_8

in

In_SOF

std_logic

in

In_EOF

std_logic

in

In_Ack

std_logic

out

Out_Valid

std_logic_vector

out

Out_Data

T_SLVV_8

out

Out_SOF

std_logic_vector

out

Out_EOF

std_logic_vector

out

Out_Ack

std_logic_vector

in

Out_Meta_DestMACAddress_rst

std_logic_vector

in

Out_Meta_DestMACAddress_nxt

std_logic_vector

in

Out_Meta_DestMACAddress_Data

T_SLVV_8

out