[source]

Entity mac_TX_SrcMAC_Prepender

DEBUGMAC_ADDRESSESClockstd_logicResetstd_logicIn_Valid[MAC_ADDRESSES ' length - 1 downto 0]std_logic_vectorIn_Data[MAC_ADDRESSES ' length - 1 downto 0]T_SLVV_8In_SOF[MAC_ADDRESSES ' length - 1 downto 0]std_logic_vectorIn_EOF[MAC_ADDRESSES ' length - 1 downto 0]std_logic_vectorIn_Meta_DestMACAddress_Data[MAC_ADDRESSES ' length - 1 downto 0]T_SLVV_8Out_Ackstd_logicOut_Meta_rststd_logicOut_Meta_DestMACAddress_nxtstd_logicIn_Ackstd_logic_vector[MAC_ADDRESSES ' length - 1 downto 0]In_Meta_rststd_logic_vector[MAC_ADDRESSES ' length - 1 downto 0]In_Meta_DestMACAddress_nxtstd_logic_vector[MAC_ADDRESSES ' length - 1 downto 0]Out_Validstd_logicOut_DataT_SLV_8Out_SOFstd_logicOut_EOFstd_logicOut_Meta_DestMACAddress_DataT_SLV_8

Block Diagram of mac_TX_SrcMAC_Prepender

Generics

Name

Type

Default

Description

DEBUG

boolean

FALSE

MAC_ADDRESSES

T_NET_MAC_ADDRESS_VECTOR

(0 => C_NET_MAC_ADDRESS_EMPTY)

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

In_Valid

std_logic_vector

in

IN Port

In_Data

T_SLVV_8

in

In_SOF

std_logic_vector

in

In_EOF

std_logic_vector

in

In_Ack

std_logic_vector

out

In_Meta_rst

std_logic_vector

out

In_Meta_DestMACAddress_nxt

std_logic_vector

out

In_Meta_DestMACAddress_Data

T_SLVV_8

in

Out_Valid

std_logic

out

OUT Port

Out_Data

T_SLV_8

out

Out_SOF

std_logic

out

Out_EOF

std_logic

out

Out_Ack

std_logic

in

Out_Meta_rst

std_logic

in

Out_Meta_DestMACAddress_nxt

std_logic

in

Out_Meta_DestMACAddress_Data

T_SLV_8

out