[source]

Entity mac_Wrapper

DEBUGMAC_CONFIGClockstd_logicResetstd_logicEth_TX_Ackstd_logicEth_RX_Validstd_logicEth_RX_DataT_SLV_8Eth_RX_SOFstd_logicEth_RX_EOFstd_logicTX_Valid[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorTX_Data[getPortCount ( MAC_CONFIG ) - 1 downto 0]T_SLVV_8TX_SOF[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorTX_EOF[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorTX_Meta_DestMACAddress_Data[getPortCount ( MAC_CONFIG ) - 1 downto 0]T_SLVV_8RX_Ack[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorRX_Meta_rst[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorRX_Meta_SrcMACAddress_nxt[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorRX_Meta_DestMACAddress_nxt[getPortCount ( MAC_CONFIG ) - 1 downto 0]std_logic_vectorEth_TX_Validstd_logicEth_TX_DataT_SLV_8Eth_TX_SOFstd_logicEth_TX_EOFstd_logicEth_RX_Ackstd_logicTX_Ackstd_logic_vector[getPortCount ( MAC_CONFIG ) - 1 downto 0]TX_Meta_rststd_logic_vector[getPortCount ( MAC_CONFIG ) - 1 downto 0]TX_Meta_DestMACAddress_nxtstd_logic_vector[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_Validstd_logic_vector[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_DataT_SLVV_8[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_SOFstd_logic_vector[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_EOFstd_logic_vector[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_Meta_SrcMACAddress_DataT_SLVV_8[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_Meta_DestMACAddress_DataT_SLVV_8[getPortCount ( MAC_CONFIG ) - 1 downto 0]RX_Meta_EthTypeT_NET_MAC_ETHERNETTYPE_VECTOR[getPortCount ( MAC_CONFIG ) - 1 downto 0]

Block Diagram of mac_Wrapper

Generics

Name

Type

Default

Description

DEBUG

boolean

FALSE

MAC_CONFIG

T_NET_MAC_CONFIGURATION_VECTOR

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Eth_TX_Valid

std_logic

out

Eth_TX_Data

T_SLV_8

out

Eth_TX_SOF

std_logic

out

Eth_TX_EOF

std_logic

out

Eth_TX_Ack

std_logic

in

Eth_RX_Valid

std_logic

in

Eth_RX_Data

T_SLV_8

in

Eth_RX_SOF

std_logic

in

Eth_RX_EOF

std_logic

in

Eth_RX_Ack

std_logic

out

TX_Valid

std_logic_vector

in

TX_Data

T_SLVV_8

in

TX_SOF

std_logic_vector

in

TX_EOF

std_logic_vector

in

TX_Ack

std_logic_vector

out

TX_Meta_rst

std_logic_vector

out

TX_Meta_DestMACAddress_nxt

std_logic_vector

out

TX_Meta_DestMACAddress_Data

T_SLVV_8

in

RX_Valid

std_logic_vector

out

RX_Data

T_SLVV_8

out

RX_SOF

std_logic_vector

out

RX_EOF

std_logic_vector

out

RX_Ack

std_logic_vector

in

RX_Meta_rst

std_logic_vector

in

RX_Meta_SrcMACAddress_nxt

std_logic_vector

in

RX_Meta_SrcMACAddress_Data

T_SLVV_8

out

RX_Meta_DestMACAddress_nxt

std_logic_vector

in

RX_Meta_DestMACAddress_Data

T_SLVV_8

out

RX_Meta_EthType

T_NET_MAC_ETHERNETTYPE_VECTOR

out