Entity ocram_sdp

Block Diagram of ocram_sdp

Inferring / instantiating simple dual-port memory, with:

• dual clock, clock enable,

• 1 read port plus 1 write port.

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

Mixed-Port Read-During-Write

When reading at the write address, the read value will be unknown which is aka. "don't care behavior". This applies to all reads (at the same address) which are issued during the write-cycle time, which starts at the rising-edge of the write clock and (in the worst case) extends until the next rising-edge of the write clock.

For simulation, always our dedicated simulation model IP:ocram_tdp_sim is used.

Generics

Name	Type	Default	Description
A_BITS	positive		number of address bits
D_BITS	positive		number of data bits
FILENAME	string	""	file-name for RAM initialization

Ports

Name	Type	Direction	Description
rclk	std_logic	in	read clock
rce	std_logic	in	read clock-enable
wclk	std_logic	in	write clock
wce	std_logic	in	write clock-enable
we	std_logic	in	write enable
ra	unsigned	in	read address
wa	unsigned	in	write address
d	std_logic_vector	in	data in
q	std_logic_vector	out	data out

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