Entity ocram_sdp_wf

Block Diagram of ocram_sdp_wf

Inferring / instantiating simple dual-port memory, with:

• single clock, clock enable,

• 1 read port plus 1 write port.

Command truth table:

ce	we	Command
0	X	No operation
1	0	Read only from memory
1	1	Read from and Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

Mixed-Port Read-During-Write

When reading at the write address, the read value will be the new data, aka. "write-first behavior". Of course, the read is still synchronous, i.e, the latency is still one clock cyle.

Generics

Name	Type	Default	Description
A_BITS	positive		number of address bits
D_BITS	positive		number of data bits
FILENAME	string	""	file-name for RAM initialization

Ports

Name	Type	Direction	Description
clk	std_logic	in	clock
ce	std_logic	in	clock-enable
we	std_logic	in	write enable
ra	unsigned	in	read address
wa	unsigned	in	write address
d	std_logic_vector	in	data in
q	std_logic_vector	out	data out

• Architecture rtl of ocram_sdp_wf
  • Functions

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