Entity ocram_tdp

Block Diagram of ocram_tdp

Inferring / instantiating true dual-port memory, with:

• dual clock, clock enable,

• 2 read/write ports.

Command truth table for port 1, same applies to port 2:

ce1	we1	Command
0	X	No operation
1	0	Read from memory
1	1	Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

Same-Port Read-During-Write

When writing data through port 1, the read output of the same port (q1) will output the new data (d1, in the following clock cycle) which is aka. "write-first behavior".

Same applies to port 2.

Mixed-Port Read-During-Write

When reading at the write address, the read value will be unknown which is aka. "don't care behavior". This applies to all reads (at the same address) which are issued during the write-cycle time, which starts at the rising-edge of the write clock and (in the worst case) extends until the next rising-edge of that write clock.

For simulation, always our dedicated simulation model IP:ocram_tdp_sim is used.

Generics

Name	Type	Default	Description
A_BITS	positive		number of address bits
D_BITS	positive		number of data bits
FILENAME	string	""	file-name for RAM initialization

Ports

Name	Type	Direction	Description
clk1	std_logic	in	clock for 1st port
clk2	std_logic	in	clock for 2nd port
ce1	std_logic	in	clock-enable for 1st port
ce2	std_logic	in	clock-enable for 2nd port
we1	std_logic	in	write-enable for 1st port
we2	std_logic	in	write-enable for 2nd port
a1	unsigned	in	address for 1st port
a2	unsigned	in	address for 2nd port
d1	std_logic_vector	in	write-data for 1st port
d2	std_logic_vector	in	write-data for 2nd port
q1	std_logic_vector	out	read-data from 1st port
q2	std_logic_vector	out	read-data from 2nd port

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