Entity ocram_tdp_altera

Block Diagram of ocram_tdp_altera

Quartus synthesis does not infer this RAM type correctly. Instead, altsyncram is instantiated directly.

For further documentation see module "ocram_tdp" (src/mem/ocram/ocram_tdp.vhdl).

Generics

Name	Type	Default	Description
A_BITS	positive
D_BITS	positive
FILENAME	string	""

Ports

Name	Type	Direction	Description
clk1	std_logic	in
clk2	std_logic	in
ce1	std_logic	in
ce2	std_logic	in
we1	std_logic	in
we2	std_logic	in
a1	unsigned	in
a2	unsigned	in
d1	std_logic_vector	in
d2	std_logic_vector	in
q1	std_logic_vector	out
q2	std_logic_vector	out

• Architecture rtl of ocram_tdp_altera
  • Components
    • Component altsyncram

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