Entity ocram_tdp_sim

Block Diagram of ocram_tdp_sim

Simulation model for true dual-port memory, with:

• dual clock, clock enable,

• 2 read/write ports.

The interface matches that of the IP core PoC.mem.ocram.tdp. But the implementation there is restricted to the description supported by various synthesis compilers. The implementation here also simulates the correct Mixed-Port Read-During-Write Behavior and handles X propagation.

Generics

Name	Type	Default	Description
A_BITS	positive		number of address bits
D_BITS	positive		number of data bits
FILENAME	string	""	file-name for RAM initialization

Ports

Name	Type	Direction	Description
clk1	std_logic	in	clock for 1st port
clk2	std_logic	in	clock for 2nd port
ce1	std_logic	in	clock-enable for 1st port
ce2	std_logic	in	clock-enable for 2nd port
we1	std_logic	in	write-enable for 1st port
we2	std_logic	in	write-enable for 2nd port
a1	unsigned	in	address for 1st port
a2	unsigned	in	address for 2nd port
d1	std_logic_vector	in	write-data for 1st port
d2	std_logic_vector	in	write-data for 2nd port
q1	std_logic_vector	out	read-data from 1st port
q2	std_logic_vector	out	read-data from 2nd port

• Architecture sim of ocram_tdp_sim
  • Functions

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