Entity ocrom_dp

Block Diagram of ocrom_dp

Inferring / instantiating dual-port read-only memory, with:

• dual clock, clock enable,

• 2 read ports.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

WARNING: The simulated behavior on RT-level is not correct.

TODO: add timing diagram TODO: implement correct behavior for RT-level simulation

Generics

Name	Type	Default	Description
A_BITS	positive
D_BITS	positive
FILENAME	string	""

Ports

Name	Type	Direction	Description
clk1	std_logic	in
clk2	std_logic	in
ce1	std_logic	in
ce2	std_logic	in
a1	unsigned	in
a2	unsigned	in
q1	std_logic_vector	out
q2	std_logic_vector	out

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