[source]

Entity ocrom_sp

A_BITSD_BITSFILENAMEclkstd_logiccestd_logica[A_BITS - 1 downto 0]unsignedqstd_logic_vector[D_BITS - 1 downto 0]

Block Diagram of ocrom_sp

Inferring / instantiating single-port read-only memory

  • single clock, clock enable

  • 1 read port

Generics

Name

Type

Default

Description

A_BITS

positive

D_BITS

positive

FILENAME

string

""

Ports

Name

Type

Direction

Description

clk

std_logic

in

ce

std_logic

in

a

unsigned

in

q

std_logic_vector

out