Package physical
For detailed documentation see below.
- NAMING CONVENTION:
t - time p - period d - delay f - frequency br - baud rate vec - vector
- ATTENTION:
This package is not supported by Xilinx Synthese Tools prior to 14.7!
- It was successfully tested with:
Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
Quartus II 13.1
QuestaSim 10.0d
GHDL 0.31
- Tool chains with known issues:
Xilinx Vivado Synthesis 2014.4
- Untested tool chains
Xilinx Vivado Simulator (xSim) 2014.4
Name |
Value |
Description |
---|---|---|
C_PHYSICAL_REPORT_TIMING_DEVIATION |
TRUE |
if true: TimingToCycles reports difference between expected and actual result |
Name |
Description |
---|---|
FREQ |
|
BAUD |
|
MEMORY |
|
T_TIMEVEC |
vector data types |
T_FREQVEC |
|
T_BAUDVEC |
|
T_MEMVEC |
Functions
- virtual function integer to_int ( time t, time scale, T_ROUNDING_STYLE RoundingStyle ) [source]
convert physical types to standard type (INTEGER)
- virtual function integer to_int ( FREQ f, FREQ scale, T_ROUNDING_STYLE RoundingStyle ) [source]
- virtual function integer to_int ( BAUD br, BAUD scale, T_ROUNDING_STYLE RoundingStyle ) [source]
- virtual function integer to_int ( MEMORY mem, MEMORY scale, T_ROUNDING_STYLE RoundingStyle ) [source]
- virtual function natural TimingToCycles ( time Timing, time Clock_Period, T_ROUNDING_STYLE RoundingStyle ) [source]
calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
- virtual function natural TimingToCycles ( time Timing, FREQ Clock_Frequency, T_ROUNDING_STYLE RoundingStyle ) [source]
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