[source]

Entity pmod_USBUART

CLOCK_FREQBAUDRATEClockstd_logicResetstd_logicTX_putstd_logicTX_Data[7 downto 0]std_logic_vectorRX_gotstd_logicUART_RXstd_logicUART_CTSstd_logicTX_Fullstd_logicRX_Validstd_logicRX_Datastd_logic_vector[7 downto 0]UART_TXstd_logicUART_RTSstd_logic

Block Diagram of pmod_USBUART

This module abstracts a FTDI FT232R USB-UART bridge by instantiating a PoC.io.uart.fifo. The FT232R supports up to 3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. Hardware flow control (RTS_CTS) is enabled.

Generics

Name

Type

Default

Description

CLOCK_FREQ

FREQ

100 MHz

BAUDRATE

BAUD

115200 Bd

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

TX_put

std_logic

in

TX_Data

std_logic_vector

in

TX_Full

std_logic

out

RX_Valid

std_logic

out

RX_Data

std_logic_vector

out

RX_got

std_logic

in

UART_TX

std_logic

out

UART_RX

std_logic

in

UART_RTS

std_logic

out

UART_CTS

std_logic

in