Entity reconfig_icap_fsm

Block Diagram of reconfig_icap_fsm

This module parses the data stream to the Xilinx "Internal Configuration Access Port" (ICAP) primitives to generate control signals. Tested on:

• Virtex-6

• Virtex-7

Ports

Name	Type	Direction	Description
clk	std_logic	in
reset	std_logic	in	high-active reset
icap_in	std_logic_vector	out	interface to connect to the icap data that will go into the icap
icap_out	std_logic_vector	in	data from the icap
icap_csb	std_logic	out
icap_rw	std_logic	out
in_data	std_logic_vector	in	data interface, no internal fifos new configuration data
in_data_valid	std_logic	in	input data is valid
in_data_rden	std_logic	out	possible to send data
out_data	std_logic_vector	out	data read from the fifo
out_data_valid	std_logic	out	data from icap is valid
out_data_full	std_logic	in	receiving buffer is full, halt icap
status	std_logic_vector	out	control structures status vector

• Architecture arch of reconfig_icap_fsm
  • Processes

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