Entity reconfig_icap_wrapper

Block Diagram of reconfig_icap_wrapper

This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) to a PCIe endpoint on a Dini board. Tested on:

tbd

Generics

Name	Type	Default	Description
MIN_DEPTH_OUT	positive	256
MIN_DEPTH_IN	positive	256

Ports

Name	Type	Direction	Description
clk	std_logic	in
reset	std_logic	in
clk_icap	std_logic	in	clock signal for ICAP, max 100 MHz (double check with manual)
icap_busy	std_logic	out	the ICAP is processing the data
icap_readback	std_logic	out	high during a readback
icap_partial_res	std_logic	out	high during reconfiguration
write_put	std_logic	in	data in
write_full	std_logic	out
write_data	std_logic_vector	in
write_done	std_logic	in	high pulse/edge after all data was written
read_got	std_logic	in	data out
read_valid	std_logic	out
read_data	std_logic_vector	out

• Architecture Behavioral of reconfig_icap_wrapper
  • Processes

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