Entity sdram_ctrl_de0

Block Diagram of sdram_ctrl_de0

Complete controller for ISSI SDR-SDRAM for Altera DE0 Board.

SDRAM Device: IS42S16400F

Configuration

Parameter	Description
CLK_PERIOD	Clock period in nano seconds. All SDRAM timings are calculated for the device stated above.
CL	CAS latency, choose according to clock frequency.
BL	Burst length. Choose BL=1 for single cycle memory transactions as required for the PoC.Mem interface.

Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1.

Operation

Command, address and write data is sampled with clk. Read data is also aligned with clk.

For description on clkout see sdram_ctrl_phy_de0.

Synchronous resets are used.

Generics

Name	Type	Default	Description
CLK_PERIOD	real
CL	positive
BL	positive

Ports

Name	Type	Direction	Description
clk	std_logic	in
clkout	std_logic	in
rst	std_logic	in
user_cmd_valid	std_logic	in
user_wdata_valid	std_logic	in
user_write	std_logic	in
user_addr	std_logic_vector	in
user_wdata	std_logic_vector	in
user_got_cmd	std_logic	out
user_got_wdata	std_logic	out
user_rdata	std_logic_vector	out
user_rstb	std_logic	out
sd_ck	std_logic	out
sd_cke	std_logic	out
sd_cs	std_logic	out
sd_ras	std_logic	out
sd_cas	std_logic	out
sd_we	std_logic	out
sd_ba	std_logic_vector	out
sd_a	std_logic_vector	out
sd_dq	std_logic_vector	inout

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