Entity sdram_ctrl_phy_de0

Block Diagram of sdram_ctrl_phy_de0

Physical layer used by module sdram_ctrl_de0.

Instantiates input and output buffer components and adjusts the timing for the Altera DE0 board.

Clock and Reset Signals

Port	Description
clk	Base clock for command and write data path.
rst	Reset for clk.

Command signals and write data are sampled with clk. Read data is also aligned with clk.

Write and read enable (wren_nxt, rden_nxt) must be hold for:

• 1 clock cycle if BL = 1,

• 2 clock cycles if BL = 2, or

• 4 clock cycles if BL = 4, or

• 8 clock cycles if BL = 8.

They must be first asserted with the read and write command. Proper delay is included in this unit.

The first word to write must be asserted with the write command. Proper delay is included in this unit.

Synchronous resets are used. Reset must be hold for at least two cycles.

Generics

Name	Type	Default	Description
CL	positive		CAS latency

Ports

Name	Type	Direction	Description
clk	std_logic	in
clkout	std_logic	in
rst	std_logic	in
sd_cke_nxt	std_logic	in
sd_cs_nxt	std_logic	in
sd_ras_nxt	std_logic	in
sd_cas_nxt	std_logic	in
sd_we_nxt	std_logic	in
sd_ba_nxt	std_logic_vector	in
sd_a_nxt	std_logic_vector	in
wren_nxt	std_logic	in
wdata_nxt	std_logic_vector	in
rden_nxt	std_logic	in
rdata	std_logic_vector	out
rstb	std_logic	out
sd_ck	std_logic	out
sd_cke	std_logic	out
sd_cs	std_logic	out
sd_ras	std_logic	out
sd_cas	std_logic	out
sd_we	std_logic	out
sd_ba	std_logic_vector	out
sd_a	std_logic_vector	out
sd_dq	std_logic_vector	inout

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