Entity sdram_ctrl_phy_s3esk

Block Diagram of sdram_ctrl_phy_s3esk

Physical layer used by module sdram_ctrl_s3esk.

Instantiates input and output buffer components and adjusts the timing for the Spartan-3E Starter Kit Board.

Clock and Reset Signals

Port	Description
clk	Base clock for command and write data path.
clk_n	clk phase shifted by 180 degrees.
clk90	clk phase shifted by 90 degrees.
clk90_n	clk phase shifted by 270 degrees.
clk_fb (on PCB)	Driven by external feedback (sd_ck_fb) of DDR-SDRAM clock (sd_ck_p). Actually unused, just referenced below.
clk_fb90	clk_fb phase shifted by 90 degrees.
clk_fb90_n	clk_fb phase shifted by 270 degrees.
rst	Reset for clk.
rst180	Reset for clk_n
rst90	Reset for clk90.
rst270	Reset for clk270.
rst_fb90	Reset for clk_fb90.
rst_fb90_n	Reset for clk_fb90_n.

Operation

Command signals and write data are sampled with the rising edge of clk.

Read data is aligned with clk_fb90_n. Either process data in this clock domain, or connect a FIFO to transfer data into another clock domain of your choice. This FIFO should capable of storing at least one burst (size BL/2) + start of next burst (size 1).

Write and read enable (wren_nxt, rden_nxt) must be hold for:

• 1 clock cycle if BL = 2,

• 2 clock cycles if BL = 4, or

• 4 clock cycles if BL = 8.

They must be first asserted with the read and write command. Proper delay is included in this unit.

The first word to write must be asserted with the write command. Proper delay is included in this unit.

The SDRAM clock is regenerated in this module. The following timing is chosen for minimum latency (should work up to 100 MHz):

• rising_edge(clk90) triggers rising_edge(sd_ck_p),

• rising_edge(clk90_n) triggers falling_edge(sd_ck_p).

XST options: Disable equivalent register removal.

Synchronous resets are used. Reset must be hold for at least two cycles.

Ports

Name	Type	Direction	Description
clk	std_logic	in
clk_n	std_logic	in
clk90	std_logic	in
clk90_n	std_logic	in
rst	std_logic	in
rst90	std_logic	in
rst180	std_logic	in
rst270	std_logic	in
clk_fb90	std_logic	in
clk_fb90_n	std_logic	in
rst_fb90	std_logic	in
rst_fb270	std_logic	in
sd_cke_nxt	std_logic	in
sd_cs_nxt	std_logic	in
sd_ras_nxt	std_logic	in
sd_cas_nxt	std_logic	in
sd_we_nxt	std_logic	in
sd_ba_nxt	std_logic_vector	in
sd_a_nxt	std_logic_vector	in
wren_nxt	std_logic	in
wdata_nxt	std_logic_vector	in
rden_nxt	std_logic	in
rdata	std_logic_vector	out
rstb	std_logic	out
sd_ck_p	std_logic	out
sd_ck_n	std_logic	out
sd_cke	std_logic	out
sd_cs	std_logic	out
sd_ras	std_logic	out
sd_cas	std_logic	out
sd_we	std_logic	out
sd_ba	std_logic_vector	out
sd_a	std_logic_vector	out
sd_ldqs	std_logic	out
sd_udqs	std_logic	out
sd_dq	std_logic_vector	inout

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