Entity sdram_ctrl_s3esk

Block Diagram of sdram_ctrl_s3esk

Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board.

SDRAM Device: MT46V32M16-6T

Configuration

Parameter	Description
CLK_PERIOD	Clock period in nano seconds. All SDRAM timings are calculated for the device stated above.
CL	CAS latency, choose according to clock frequency.
BL	Burst length. Choose BL=2 for single cycle memory transactions as required for the PoC.Mem interface.

Tested with: CLK_PERIOD = 10.0, CL=2, BL=2.

Operation

Command, address and write data are sampled with the rising edge of clk.

Read data is aligned with clk_fb90_n. Either process data in this clock domain, or connect a FIFO to transfer data into another clock domain of your choice. This FIFO should capable of storing at least one burst (size BL/2) + start of next burst (size 1).

Synchronous resets are used.

Generics

Name	Type	Default	Description
CLK_PERIOD	real
BL	positive

Ports

Name	Type	Direction	Description
clk	std_logic	in
clk_n	std_logic	in
clk90	std_logic	in
clk90_n	std_logic	in
rst	std_logic	in
rst90	std_logic	in
rst180	std_logic	in
rst270	std_logic	in
clk_fb90	std_logic	in
clk_fb90_n	std_logic	in
rst_fb90	std_logic	in
rst_fb270	std_logic	in
user_cmd_valid	std_logic	in
user_wdata_valid	std_logic	in
user_write	std_logic	in
user_addr	std_logic_vector	in
user_wdata	std_logic_vector	in
user_got_cmd	std_logic	out
user_got_wdata	std_logic	out
user_rdata	std_logic_vector	out
user_rstb	std_logic	out
sd_ck_p	std_logic	out
sd_ck_n	std_logic	out
sd_cke	std_logic	out
sd_cs	std_logic	out
sd_ras	std_logic	out
sd_cas	std_logic	out
sd_we	std_logic	out
sd_ba	std_logic_vector	out
sd_a	std_logic_vector	out
sd_ldqs	std_logic	out
sd_udqs	std_logic	out
sd_dq	std_logic_vector	inout

×