[source]

Entity stat_Average

DATA_BITSCOUNTER_BITSClockstd_logicResetstd_logicEnablestd_logicDataIn[DATA_BITS - 1 downto 0]std_logic_vectorCountstd_logic_vector[COUNTER_BITS - 1 downto 0]Sumstd_logic_vector[COUNTER_BITS - 1 downto 0]Averagestd_logic_vector[COUNTER_BITS - 1 downto 0]Validstd_logic

Block Diagram of stat_Average

Generics

Name

Type

Default

Description

DATA_BITS

positive

8

COUNTER_BITS

positive

16

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Enable

std_logic

in

DataIn

std_logic_vector

in

Count

std_logic_vector

out

Sum

std_logic_vector

out

Average

std_logic_vector

out

Valid

std_logic

out