Component sync_Bits_Altera

Block Diagram of sync_Bits_Altera

Generics

Name	Type	Initial Value	Description
BITS	positive	1	number of bit to be synchronized
INIT	std_logic_vector	x"00000000"	initialization bits
SYNC_DEPTH	T_MISC_SYNC_DEPTH	low	generate SYNC_DEPTH many stages, at least 2

Ports

Name	Direction	Type	Description
Clock	in	std_logic	Clock to be synchronized to
Input	in	std_logic_vector	Data to be synchronized
Output	out	std_logic_vector	synchronized data

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